Access circuit for central processors of digital communication system

Claim 2

A programmable digital data processing system including first and second data processors, each having processing circuits, maintenance circuits, a plurality of internal sense circuit points in said processing and maintenance circuits and a plurality of internal control circuit points in said processing and maintenance circuits, each of said data processors being responsive to a read maintenance instruction and a write maintenance instruction, each of said instructions including address signals representative of preselected ones of said control and sense circuit points, said data processors cooperating such that only one data processor is active and the other is passive at any one time, wherein the improvement comprises: maintenance access circuit means in each of said processors, each including maintenance access circuit means internal conductive bus means including an internal maintenance select bus, an internal maintenance data bus and an internal maintenance return bus, said buses coupling said maintenance access circuit means with said selected circuit points in its associated data processor; addressing and gating control circuit means responsive to maintenance address signals in said instructions for communicating said maintenance access circuit means along said internal select but with selected ones of said control or sense circuit points represented by said address signals in an associated maintenance instruction; first gate means at each of said selected circuit points responsive to said maintenance address signals in a write maintenance instruction and a data signal on said internal data bus for writing the associated data signal to each selected control circuit point; second gate means at each of said sense circuit points responsive to said maintenance address signals in a read maintenance instruction and a sense data signal at an associated sense point for coupling said sense data signal to said return bus; and a return data buffer register circuit for receiving sensed data signals from said return bus in response to a read maintenance instruction for temporarily storing said sensed data signals for use by said data processor; and external conductive bus means comprising an external maintenance select bus, an external maintenance data bus and an external maintenance return bus, all of said external buses interconnecting only both of said maintenance access circuit means for coupling address, data and return signals therebetween in response to said maintenance instructions.

Claim 3

The system of claim 1 wherein the active one of said data processors generates an active level signal only when active and wherein said maintenance instructions include signals representative of addresses for the active and standby processors, and wherein said addressing and gating control circuit means of said maintenance access circuit means is responsive only to the active level signal of its associated processor and is responsive to the active select and standby select signals of said instruction words, said maintenance access circuit means further including select circuit means for selectively addressing either said active processor only, said standby processor only, or both said active and standby processors in response to said active and passive select signals of said instruction words.

Claim 4

The system of claim 2 wherein said select circuit means includes a first standby select gate responsive only to said standby select signals of said instruction word and a second active selEct gate responsive only to said active select signals of said instruction words; and wherein said external select bus includes a first external select bus communicating said standby select gate with the maintenance access circuit means in the other central processor and a second external select bus coupling said active select gate with the maintenance access circuit means in its own processor.

Claim 5

The system of claim 3 wherein each of said external bus means is an alternating current bus system and wherein each of said internal maintenance buses is a direct current bus system, wherein the active central processor has access to the maintenance access circuit means of the standby central processor even though the standby central processor is stopped but with power on.

Claim 6

A programmable digital data processor system including first and second data processors, each having processing circuits, maintenance circuits, a plurality of internal sense circuit points in said processing and maintenance circuits and a plurality of internal control circuit points in said processing and maintenance circuits, each of said data processors being responsive to a read maintenance instruction and a write maintenance instruction, each of said instructions including address signals representative of preselected ones of said control and sense circuit points, said address signals including X-select and Y-select address signals, said address signals further including an active select signal and a standby select signal, said data processor cooperating such that only one data processor is active and the other is standby at one time, wherein the improvement comprises: maintenance access circuit means in each of said processors, each maintenance access circuit means including maintenance access circuit means for writing data signals and selected ones of said control circuit points in response to a write maintenance instruction and for reading output signals from selected ones of said sense circuit points in response to a read maintenance instruction, said maintenance access circuit including internal conductive bus means including an internal maintenance select bus, an internal maintenance data bus and an internal maintenance return bus coupling said maintenance access circuit means with said selected circuit points in its associated data processor; addressing and gating control circuit means including a standby select gate means, an active select gate means and an X-select gate means, said standby select gate means and said active select gate means receiving the Y-select address signals and responsive respectively to active select and standby select signals in said instruction, said Y-select gate means receiving the Y-select address signals of said instructions; gate means at each of said select circuit points responsive to said maintenance address signals in a write maintenance instruction and an internal data bus for writing the associated data signal to each selected control circuit point; second gate means at each of said sense circuit points responsive to said maintenance address signals in a read maintenance instruction and a sense data signal at an associated sense point for coupling said sense data signal to said return bus; and a return data buffer register circuit for receiving sensed data signals from said internal return bus in response to a read maintenance instruction for temporarily storing said sensed data signals for use by said data processor; external conductive bus means including an external maintenance select bus, an external maintenance data bus and an external maintenance return bus, said external maintenance select bus including a first bus coupling the Y-select address signals of said active select gate means of a first maintenance access circuit means and the Y-select address signals of said standby select gate means of the other maintenance access circuit means to the internal maintenance select bus of said first maintenance access circuit; a second bus coupling the Y-select address signals of said active select gate means of said other maintenance access circuit means and the Y-select address signals of said standby select gate means of said first maintenance access circuit means to the internal maintenance select bus of said other maintenance access circuit means; and a third bus coupling the outputs of said X-select gate means of both maintenance access circuit means to both of said internal maintenance select buses; whereby the maintenance access circuit means in the active data processor may address the circuit points in either the active data processor only, the standby data processor only, or both the active and standby data processors without regard to which of the data processors is active or standby at the time.

Claim 7

A programmable digital data processor system including first and second data processors, each having processing circuits, maintenance circuits, a plurality of internal sense circuit points in said processing and maintenance circuits and a plurality of internal control circuit points in said processing and maintenance circuits, each of said data processors being responsive to a read maintenance instruction and a write maintenance instruction, each of said instructions including address signals representative of preselected ones of said control and sense circuit points, said address signals including X-select and Y-select address signals, said address signals further including an active select signal and a standby select signal, said data processor cooperating such that only one data processor is active and the other is standby at one time, wherein the improvement comprises: maintenance access circuit means in each of said processors, each maintenance access circuit means including maintenance access circuit means for writing data signals and selected ones of said control circuit points in response to a write maintenance instruction and for reading output signals from selected ones of said sense circuit points in response to a read maintenance instruction, said maintenance access circuit including internal conductive bus means including an internal maintenance select bus, an internal maintenance data bus and an internal maintenance return bus coupling said maintenance access circuit means with said selected circuit points in its associated data processor; addressing and gating control circuit means including a standby select gate means, an active select gate means and an X-select gate means, said standby select gate means and said active select gate means receiving the Y-select address signals and responsive respectively to active select and standby select signals in said instruction, said Y-select gate means receiving the Y-select address signals of said instructions; gate means at each of said select circuit points responsive to said maintenance address signals in a write maintenance instruction and an internal data bus for writing the associated data signal to each selected control circuit point; second gate means at each of said sense circuit points responsive to said maintenance address signals in a read maintenance instruction and a sense data signal at an associated sense point for coupling said sense data signal to said return bus; and a return data buffer register circuit for receiving sensed data signals from said internal return bus in response to a read maintenance instruction for temporarily storing said sensed data signals for use by said data processor; external conductive bus means including an external maintenance select bus, an external maintenance data bus and an external maintenance return bus, said external maintenance select bus including a first bus coupling the Y-select address signals of said active select gate means of a first maintenance access circuit means and the Y-select address signals of said standby select gate means of the other maintenance access circuit means to the internal maintenance select bus of said first maintenance access circuit; a second bus coupling the Y-select address signals of said active select gate means of said other maintenance access circuit means and the Y-select address signals of said standby select gate means of said first maintenance access circuit means to the internal maintenance select bus of said other maintenance access circuit means; and a third bus coupling the outputs of said X-select gate means of both maintenance access circuit means to both of said internal maintenance select buses; whereby the maintenance access circuit means in the active data processor may address the circuit points in either the active data processor only, the standby data processor only, or both the active and standby data processors without regard to which of the data processors is active or standby at the time.

Claim 8

A programmable digital data processing system including first and second data processors, each having processing circuits, maintenance circuits, a plurality of internal sense circuit points in said processing system and maintenance circuits and a plurality of internal control circuit points in said processing and maintenance circuits, each of said data processors being responsive to a read maintenance instruction and a write maintenance instruction, each of said instructions including X-select address signals and Y-select address signals, the conicidence of which represents preselected ones of said control and sense circuit points, said data processors cooperating such that only one data processor is active and the other is standby at any one time, the active data processor generating an activity level signal, wherein the improvement comprises: maintenance access circuit means in each of said processors, each maintenance access circuit means including internal conductive bus means including an internal maintenance select bus, an internal maintenance data bus, internal maintenance return bus coupling said maintenance access circuit means with said selected circuit points in its associated data processor; addressing and gating circuit means responsive to maintenance address signals in said instructions for communicating said maintenance access circuit means with external conductive bus means; gate means in each of said selected circuit points responsive to said maintenance address signals in a write maintenance instruction and the data signal on said internal data bus for writing the associated data signal to each selected control circuit point; second gate means at each of said sense circuit points responsive to said maintenance address signals in a read maintenance instruction and a sense data signal at an associated sense point for coupling said sense data signal to said return bus; and a return data buffer register circuit for receiving sensed data signals from said return bus in response to a read maintenance instruction for temporarily storing said sensed data signals for use by its associated data processor; and external AC conductive bus means including an external maintenance select bus, an external maintenance data bus, and an external maintenance return bus interconnecting only both of said maintenance access circuit means for coupling address, data and return signal pulses therebetween in response to said maintenance instructions, the coincidence of address pulses transmitted to the standby processor gating the information in the associated sense circuit points in said standby processor onto the internal maintenance return bus of said central processor and thence along said AC external maintenance return bus to said return data buffer register circuit of said active maintenance access circuit means, said sensing action in said standby processor being dependent only upon the coincidence of said X-select and Y-select address signals and power at said standby processor.

Claim 9

A programmable digital data processing system including first and second data processors, each having processing circuits, maintenance circuits, a plurality of internal sense circuit points in said processing system and maintenance circuits and a plurality of internal control circuit points in said processing and maintenance circuits, each of said data processors being responsive to a read maintenance instruction and a write maintenance instruction, each of said instructions including X-select address signals and Y-select address signals, the conicidence of which represents preselected ones of said control and sense circuit points, said data processors cooperating such that only one data processor is active and the other is standby at any one time, the active data processor generating an activity level signal, wherein the improvement comprises: maintenance access circuit means in each of said processors, each maintenance access circuit means including internal conductive bus means including an internal maintenance select bus, an internal maintenance data bus, internal maintenance return bus coupling said maintenance access circuit means with said selected circuit points in its associated data processor; addressing and gating circuit means responsive to maintenance address signals in said instructions for communicating said maintenance access circuit means with external conductive bus means; gate means in each of said selected circuit points responsive to said maintenance address signals in a write maintenance instruction and the data signal on said internal data bus for writing the associated data signal to each selected control circuit point; second gate means at each of said sense circuit points responsive to said maintenance address signals in a read maintenance instruction and a sense data signal at an associated sense point for coupling said sense data signal to said return bus; and a return data buffer register circuit for receiving sensed data signals from said return bus in response to a read maintenance instruction for temporarily storing said sensed data signals for use by its associated data processor; and external AC conductive bus means including an external maintenance select bus, an external maintenance data bus, and an external maintenance return bus interconnecting only both of said maintenance access circuit means for coupling address, data and return signal pulses therebetween in response to said maintenance instructions, the coincidence of address pulses transmitted to the standby processor gating the information in the associated sense circuit points in said standby processor onto the internal maintenance return bus of said central processor and thence along said AC external maintenance return bus to said return data buffer register circuit of said active maintenance access circuit means, said sensing action in said standby processor being dependent only upon the coincidence of said X-select and Y-select address signals and power at said standby processor.

Claim 10

A programmable digital data processor system including first and second data processorS, each having processing circuits, maintenance circuits, a plurality of internal sense circuit points in said processing and maintenance circuits and a plurality of internal control circuit points in said processing and maintenance circuits, each of said data processors being responsive to a read maintenance instruction and a write maintenance instruction, each of said instructions including address signals representative of preselected ones of said control and sense circuit points, said address signals including an active select signal and a standby select signal, each of said data processors cooperating such that only one data processor is active and the other is standby at one time, wherein the improvement comprises: maintenance access circuit means in each of said data processors for writing data signals at selected ones of said control circuit points in response to a write maintenance instruction and for reading output signals from selected ones of said sense circuit points in response to a read maintenance instruction; external bus means comprising address conductors and data conductors with connections only to said maintenance access circuit means of both of said data processors; input address gate means in the maintenance access circuit means of each data processor with means effective in the active data processor to supply signals to said address conductors of the external bus in accordance with the address signals of said maintenance instructions, with at least some of the address signals supplied to different address conductors depending on the active select signal and standby select signal; means coupling the external bus means via receiving means of the maintenance access circuits in each data processor to said internal sense circuit points and internal control circuit points for executing said maintenance instructions selecting said points in either the active or the standby data processor according to said active select signal or said standby select signal being present in the instruction.

Claim 11

A programmable digital data processor system including first and second data processorS, each having processing circuits, maintenance circuits, a plurality of internal sense circuit points in said processing and maintenance circuits and a plurality of internal control circuit points in said processing and maintenance circuits, each of said data processors being responsive to a read maintenance instruction and a write maintenance instruction, each of said instructions including address signals representative of preselected ones of said control and sense circuit points, said address signals including an active select signal and a standby select signal, each of said data processors cooperating such that only one data processor is active and the other is standby at one time, wherein the improvement comprises: maintenance access circuit means in each of said data processors for writing data signals at selected ones of said control circuit points in response to a write maintenance instruction and for reading output signals from selected ones of said sense circuit points in response to a read maintenance instruction; external bus means comprising address conductors and data conductors with connections only to said maintenance access circuit means of both of said data processors; input address gate means in the maintenance access circuit means of each data processor with means effective in the active data processor to supply signals to said address conductors of the external bus in accordance with the address signals of said maintenance instructions, with at least some of the address signals supplied to different address conductors depending on the active select signal and standby select signal; means coupling the external bus means via receiving means of the maintenance access circuits in each data processor to said internal sense circuit points and internal control circuit points for executing said maintenance instructions selecting said points in either the active or the standby data processor according to said active select signal or said standby select signal being present in the instruction.

Claim 12

The processor system of claim 7, wherein at least a portion of the address conductors of the external bus means are duplicated in a first set and a second set; wherein in said first data processor said input address gate means includes gate means enabled responsive to the active select signal to couple address signals to the first set and gate means enabled responsive to the standby select signal to couple the same address signals to the second set; and in said second data processor said input address gate means includes corresponding gate means enabled respectively responsive to the active select signal and standby select signal to couple corresponding address signals to the second set or first set respectively; the input address gate means being enabled only in the active data processor; wherein said first set of address conductors is coupled via said receiving means only in the first data processor and the second set is coupled via receiving means only in the second data processor, the data conductors and remaining address conductors being coupled via receiving means in both data processors.