US3659273A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error checking arrangement
Assignee: International Business Machines Corp
•
Filing: 1970-05-26
•
Granted: 1972-04-25
•
Expires: 1990-05-26
Abstract
Abstract This disclosure is for a rearrangement of the input/output controls of a small central processing unit (CPU) to enable interspersed use of the input/output devices by the CPU and by the customer engineer. This configuration allows the engineer to read the status of the devices and to test their functions without interference with the CPU usage of the devices and without shutting down of the system.
Inventors
- 👤 Gunter Knauft
- 👤 Fritz Koederitz
- 👤 Helmut Painke
- 👤 Leopold Reichl
- 👤 Hans H Lampe
- 👤 Robert Vachenauer
- 👤 Edwin Vogt
- 👤 Hermann Weber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:39
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2221; G06F13/00; G06F13/38; G06F13/42; G06F13/4247; G06F11/2236; G06F11/2268; G06F11/2294
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
172 words
In a data processing system of the type having a central processing unit with a plurality of attachment control units for input/output devices connected thereto by a common address bus and a common data bus, said central processing unit also including an operator control unit, an instruction decoding device to apply signals to said buses and a system stopping control, the combination of a second address bus controlled by settable members on said operator control unit and settable to the address of one of said attachment control units, a switch to connect the common address bus to either said central processing unit or to said second address bus and a switch control unit responsive to the position of another settable member on said operator control panel and to said instruction decoding device when input/output control instructions are not being decoded to operate said switch from the normal position connecting said common address bus to said instruction decoding device to a test position connecting said common address bus to said second address bus.
Claim 2
Dependent Claim
172 words
In a data processing system of the type having a central processing unit with a plurality of attachment control units for input/output devices connected thereto by a common address bus and a common data bus, said central processing unit also including an operator control unit, an instruction decoding device to apply signals to said buses and a system stopping control, the combination of a second address bus controlled by settable members on said operator control unit and settable to the address of one of said attachment control units, a switch to connect the common address bus to either said central processing unit or to said second address bus and a switch control unit responsive to the position of another settable member on said operator control panel and to said instruction decoding device when input/output control instructions are not being decoded to operate said switch from the normal position connecting said common address bus to said instruction decoding device to a test position connecting said common address bus to said second address bus.
Claim 3
Dependent Claim
61 words
The processing system as set out in claim 1 including a set of indicators at said operator control unit and circuits in said central processing unit responsive when said input/output instructions are not be decoded to information on said common data bus to selectively operate said indicators to indicate the data received from an addressed one of said attachment control units.
Claim 4
Dependent Claim
102 words
A data processing system of the type set out in claim 1 in which said central processing unit includes a stop control settable by a control signal, a comparing device to receive the data on said common data bus, other settable devices on said operator control unit to transmit to said comparing device a desired data combination and a circuit energized when said instruction decoding device does not decode selected input/output instructions to activate said comparing device and a switch closed by said switch control unit to connect the output of said comparing device as a control signal to said stop control.
References Cited (Backward Citations)
US3343141A
Cited
US3387262A
Cited
US3405395A
Cited
US3387276A
Cited
US3488634A
Cited
US3510843A
Cited
US3518413A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-25 | 1975-10-25 | 1976-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-25 | 1979-10-25 | 1980-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-25 | 1983-10-25 | 1984-04-25 | $7700.00 | Window Closed / Lapsed |