US3646519A
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US
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Method and apparatus for testing logic functions in a multiline data communication system
Assignee: Unisys Corp
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Filing: 1970-02-02
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Granted: 1972-02-29
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Expires: 1990-02-02
Abstract
Abstract A data communication system in which a single control logic function is tested by writing a test control word for one communication line into a time-shared control circuit register from a processor. The control word together with a test line input word generated by the processor are coupled to the control logic for one clock period to perform one step of the logic function, the result being stored in memory. The result is then interrogated in memory to determine if the result of the logic function meets the test.
Inventors
- 👤 James E Wollum
- 👤 Robert L Rawlings
- 👤 James Clark Davidson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:39
CPC Classifications
H; H04; H04L; H04L43/00; H04L43/50; Y; Y04; Y04S; Y04S40/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
325 words
In a time-shared multiline control for controlling the transfer of data between a plurality of communication lines and a processor, wherein storage means having a plurality of storage locations storing control words is periodically scanned to transfer each of the control words in repetitive sequence from the storage means to a control word register and the communication lines are scanned in synchronism with the scanning of the storage locations to couple each of the lines in repetitive sequence to an input register and an output register, the contents of the input register and control word register being applied to the input of a logic circuit, the output of the logic circuit normally being coupled to each of the storage locations in the same repetitive sequence to replace each of the control words in a modified condition determined by the condition of the inputs to the logic circuit, test apparatus for testing the multiline control by the processor comprising: means responsive to the processor for loading a first test word in the control register from the processor in place of a control word transferred from the output of the storage means, bypassing means responsive to a predetermined bit in the first test word when in the control register for directly coupling the word in the control register to the storage means in place of the output of the logic circuit when the test bit is set to a first condition, whereby the first test word is written into a storage location in the storage means for loading a second test word in the input register from the processor simultaneously with the transfer of the first test word from the storage means to the control word register, and means sensing when the first test word is in the control register and the second test word is in the input register for disabling said bypassing means and loading the storage means from the output of the logic circuit.
Claim 2
Dependent Claim
325 words
In a time-shared multiline control for controlling the transfer of data between a plurality of communication lines and a processor, wherein storage means having a plurality of storage locations storing control words is periodically scanned to transfer each of the control words in repetitive sequence from the storage means to a control word register and the communication lines are scanned in synchronism with the scanning of the storage locations to couple each of the lines in repetitive sequence to an input register and an output register, the contents of the input register and control word register being applied to the input of a logic circuit, the output of the logic circuit normally being coupled to each of the storage locations in the same repetitive sequence to replace each of the control words in a modified condition determined by the condition of the inputs to the logic circuit, test apparatus for testing the multiline control by the processor comprising: means responsive to the processor for loading a first test word in the control register from the processor in place of a control word transferred from the output of the storage means, bypassing means responsive to a predetermined bit in the first test word when in the control register for directly coupling the word in the control register to the storage means in place of the output of the logic circuit when the test bit is set to a first condition, whereby the first test word is written into a storage location in the storage means for loading a second test word in the input register from the processor simultaneously with the transfer of the first test word from the storage means to the control word register, and means sensing when the first test word is in the control register and the second test word is in the input register for disabling said bypassing means and loading the storage means from the output of the logic circuit.
Claim 3
Dependent Claim
208 words
Apparatus for testing a logic function of a logic circuit receiving a plurality of input bits and generating a plurality of output bits, comprising: means for storing a first group of bits, means for periodically reading out said first group of bits from the storing means, means for sensing a predetermined bit pattern in the group of bits as they are read out of the storing means, means applying the bits read out of the storing means to the logic circuit, means responsive to the sensing means when said predetermined bit pattern is not present for storing the resulting output of the logic circuit in the storage means in place of said first group of bits, means responsive to said sensiNg means when the predetermined bit pattern is present for bypassing the logic circuit and restoring the first group of bits to the storage means, means for applying a second group of bits to the logic circuit, and means responsive to a test signal and the sensing means when said predetermined bit pattern is present in the first group of bits read out of the storage means for storing the resulting output of the logic circuit in the storage means in place of said first group of bits.
Claim 4
Dependent Claim
208 words
Apparatus for testing a logic function of a logic circuit receiving a plurality of input bits and generating a plurality of output bits, comprising: means for storing a first group of bits, means for periodically reading out said first group of bits from the storing means, means for sensing a predetermined bit pattern in the group of bits as they are read out of the storing means, means applying the bits read out of the storing means to the logic circuit, means responsive to the sensing means when said predetermined bit pattern is not present for storing the resulting output of the logic circuit in the storage means in place of said first group of bits, means responsive to said sensiNg means when the predetermined bit pattern is present for bypassing the logic circuit and restoring the first group of bits to the storage means, means for applying a second group of bits to the logic circuit, and means responsive to a test signal and the sensing means when said predetermined bit pattern is present in the first group of bits read out of the storage means for storing the resulting output of the logic circuit in the storage means in place of said first group of bits.
Claim 5
Independent Claim
223 words
A system for testing time-shared control logic in a data communication system in which a plurality of separate line control words are continuously scanned to service a plurality of communication lines, comprising: a register, a storage device for storing said line control words in a plurality of storage locations, means for transferring each of said control words from said storage locations in repetitive sequence to the register, a logic circuit having an input connected to the output of said register for generating an output condition in response to the contents of the register, whereby each control word in the register generates an output from the logic circuit, means synchronized with said transferring means for writing into each of the storage locations in repetitive sequence from a common input, switching means for selectively connecting either the output of the register or the output of the logic circuit to the common input of the writing means, means responsive to a predetermined bit condition in a control word in the register for controlling the switching means to couple the output of the register directly to the input of the writing means, and means responsive to said predetermined bit condition in the register and a control signal for controlling the switching means to couple the output of the logic circuit to the input of the writing means.
Claim 6
Independent Claim
223 words
A system for testing time-shared control logic in a data communication system in which a plurality of separate line control words are continuously scanned to service a plurality of communication lines, comprising: a register, a storage device for storing said line control words in a plurality of storage locations, means for transferring each of said control words from said storage locations in repetitive sequence to the register, a logic circuit having an input connected to the output of said register for generating an output condition in response to the contents of the register, whereby each control word in the register generates an output from the logic circuit, means synchronized with said transferring means for writing into each of the storage locations in repetitive sequence from a common input, switching means for selectively connecting either the output of the register or the output of the logic circuit to the common input of the writing means, means responsive to a predetermined bit condition in a control word in the register for controlling the switching means to couple the output of the register directly to the input of the writing means, and means responsive to said predetermined bit condition in the register and a control signal for controlling the switching means to couple the output of the logic circuit to the input of the writing means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-02-28 | 1975-08-30 | 1976-02-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-02-28 | 1979-08-30 | 1980-02-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-02-28 | 1983-08-30 | 1984-02-29 | $7700.00 | Window Closed / Lapsed |