Fault detection and isolation in computer input-output devices

Claim 2

Fault detection apparatus for determining the operability of a plurality of contact closure output switches during operation, each having a first state of operation and a second state of operation, said apparatus being operative with a digital computer including an instruction program in accordance with a desired state of operation for each of said switch, comprising: first means for sending a signal to each said switch; second means for sensing the state of operation of each said switches; and third means for providing the information as to the state of each of said switches to the computer for comparison with said instruction program to determine the operative state of each of said contact closure output switches.

Claim 3

Apparatus of claim 1 wherein the second means comprises: an input adapted to be connected with a DC voltage source; first electrical conductive paths between said input and said switches being tested; and second electrical conductive paths between said switches and the second means.

Claim 4

Apparatus of claim 2 wherein said second means and third means comprises a plurality of contact input isolation test circuits, each having an input connected to one of said switches during a predetermined state of operation, and an output adapted to be connected with the computer to send a first binary signal to the computer whenever there is a signal through said switch and second binary signal whenever there is a lack of a signal through said switch.

Claim 5

The apparatus of claim 3 including multiplexing means coupled between said switches and said second means wherein a plurality of said switches may be sensed by a smaller plurality of said contact input isolation test circuits.

Claim 6

Apparatus of claim 4 wherein the contact closure output switches are arranged in a plurality of contact closure output modules and said contact input isolation test circuits are arranged in a contact input buffer module.

Claim 7

A system as in claim 5 wherein fault isolation means are coupled to said contact closure output modules respectively to provide isolation for any of said contact closure output modules whenever it is determined that a faulty contact closure output switch is located therein.

Claim 8

A system as in claim 5 wherein the multiplexing means comprises a plurality of normally closed multiplexing switches, each of said switches having a back contact and being associated with a contact closure output module and each having first and second terminals, the first being connected to ground; a plurality of diodes each having its forward terminal connected with an input of one of said plurality of contact input isolation circuits and having its blocking terminal connected to the second terminal of said multiplexing switch, and wherein any signals through the back contacts of any contact closure output module are directed fRom the inputs of the contact input isolation test circuits to ground whenever the corresponding multiplexing switch is closed.

Claim 9

A system as in claim 6 wherein the contact closure output switches are arranged in parallel within each of said plurality of contact closure output modules so as to require a single electrical path from said signal sending means to each module and wherein said fault isolation means comprises a normally closed fault isolation contact switch interposed between said input and each of said plurality of contact closure output modules to isolate any contact closure output module having a faulty contact closure output switch thereon from said signal sending means and thereby permitting the removal of the faulty contact closure output module from the system.

Claim 10

A system as in claim 3 including means coupled to said isolation test circuits for checking the electrical integrity of the contact input isolation test circuits.

Claim 11

A system as in claim 9 wherein the contact input isolation test circuits integrity checking means comprises: a plurality of test diodes corresponding in number to said plurality of contact input isolation test circuits, each having a forward terminal and a blocking terminal, each blocking terminal being connected to the input of one of said plurality of contact input isolation test circuits; a normally open test switch having first and second terminals, its first terminal being connected to the forward terminals of said plurality of test diodes and its second terminal being connectable with a direct current voltage supply such that when said test switch is closed current will be received at the inputs of said contact input isolation circuits and wherein the output response of each of said contact input isolation circuits will be a binary ''''ONE'''' if operable and a binary ''''ZERO'''' if inoperable.

Claim 12

A system as in claim 10 including an additional isolation test circuit having an input and an output, and wherein the input is connected to the diode side of said normally open test switch such that whenever said test switch is open the output of said additional isolation test circuit will provide a binary ''''ZERO'''' signal if said diodes and said test switch are operable and will provide a binary ''''ONE'''' signal whenever either one is inoperable.

Claim 13

In a computer-controlled process having a plurality of contact input isolation circuits, each having an input for receiving binary signals resulting from opening and closing one of a plurality of input switches connectable with a DC power source and located within the process, and an output for providing a first binary digit when no input signal is received and a second binary digit when an input signal is received, a system for detecting faults in the contact input isolation circuits comprising: means for isolating the input of each of said plurality of contact input isolation circuits from the binary signals transmitted through the plurality of input switches; means for monitoring the outputs of the plurality of contact input isolation circuits, wherein it can be determined that a contact input isolation circuit is inoperable if a second binary digit is read; means for providing a test signal to each input of the plurality of contact input isolation circuits; means for monitoring each of the outputs of the plurality of contact input isolation circuits wherein it can be determined that a contact input isolation circuit is inoperable if a first binary digit is read.

Claim 14

In a computer-controlled process having a plurality of contact input isolation circuits, each having an input for receiving binary signals resulting from opening and closing one of a plurality of input switches connectable with a DC power source and located within the process, and an output for providing a first binary digit when no input signal is received and a second binary digit when an input signal is received, a system for detecting faults in the contact input isolation circuits comprising: means for isolating the input of each of said plurality of contact input isolation circuits from the binary signals transmitted through the plurality of input switches; means for monitoring the outputs of the plurality of contact input isolation circuits, wherein it can be determined that a contact input isolation circuit is inoperable if a second binary digit is read; means for providing a test signal to each input of the plurality of contact input isolation circuits; means for monitoring each of the outputs of the plurality of contact input isolation circuits wherein it can be determined that a contact input isolation circuit is inoperable if a first binary digit is read.

Claim 15

A system as in claim 12 wherein the plurality of input switches are arranged in parallel array respectively, to form a lesser number of input switch groups, wherein the contact input isolation circuits are arranged to form a contact input buffer module having a common input terminal, wherein the isolation means comprises means for opening all of a plurality of multiplexing switches, each of which is connected in series between the common input terminal of oNe of said contact input buffer modules and the DC power source, such that whenever a multiplexing switch is closed the binary signals are transmitted to the contact input buffer module from the input switch group associated with it.

Claim 16

A system as in claim 12 wherein the test signal providing means comprises: a normally open test switch having first and second terminals, the first terminal being connectable with a direct current voltage source; a plurality of diodes corresponding to the number of contact input isolation circuits, each having a forward terminal connected to the second terminal of said test switch and each having a blocking terminal connected to the input of one of said plurality of contact input isolation circuits; such that whenever said test switch is closed a signal is provided to the inputs of each of the contact input isolation circuits.

Claim 17

A system as in claim 14 including means for determining the integrity of the test signal providing means comprising a test signal input isolation circuit, having an input connected with the second terminal of said test switch and an output which provides a binary ''''ZERO'''' output signal whenever there is an absence of a signal at the input and a binary ''''ONE'''' output signal when there is a signal at the input, such that if a binary ''''ONE'''' signal is provided at the output of said test signal input isolation circuit when said test switch is ordered open, it is indicative that one of the elements of said test signal providing means is inoperable.

Claim 18

A system as in claim 13 for determining the operability of said plurality of multiplexing switches comprising: test multiplexing input isolation circuit, having an input and an output, the output providing a binary ''''ZERO'''' output signal whenever there is an absence of a signal at the input and a binary ''''ONE'''' output signal when there is a signal at the input; a plurality of diodes corresponding in number to the plurality of multiplexing switches, each diode having an anode terminal and a cathode terminal, each of the anode terminals being connected with a multiplexing switch and each of the cathode terminals being connected with the input of said test multiplexing input isolation circuit; whereas if a binary ''''ONE'''' output signal is provided at the output of said test multiplexing input isolation circuit when all of said plurality of multiplexing switches are ordered open, it is indicative that one of said multiplexing switches is inoperable.

Claim 19

A system as in claim 10 for determining the operability of the contact input isolation test circuit integrity checking means comprising: a test sensing and relaying input isolation circuit, having an input and an output, the output providing a binary ''''ZERO'''' output signal whenever there is an absence of a signal at the input and a binary ''''ONE'''' output signal when there is a signal at the input; the input being connected to the anode terminal of said plurality of test diodes, whereas, if a binary ''''ONE'''' output signal is provided at the output of said test sensing and relaying input isolation circuit when said test relay is ordered open, it is indicative that one of the elements of said contact input isolation test circuit integrity checking means is inoperable.

Claim 20

In a computer control apparatus having a plurality of priority interrupt circuits, each having an input for receiving binary signals resulting from opening and closing one of a plurality of input switches connectable with a DC power source and located within the process, and an output for sending a first binary signal when no input signal is received and a second binary signal when an input signal is received, a system for detecting faults in the priority interrupt isolation circuits comprising: means for isolating the input of each of said plurality of priority interrupt circuits from the binary signals transmitted through the plurality of input switChes; means for reading the outputs of the plurality of priority interrupt circuits, wherein it can be determined that a priority interrupt circuit is operable if a second binary signal is read; means for providing a test signal to each input of the plurality of priority interrupt circuits; means for reading each of the outputs of the plurality of priority interrupt circuits wherein it can be determined that a priority interrupt circuit is inoperable if a first binary signal is read.

Claim 21

In a computer control apparatus having a plurality of priority interrupt circuits, each having an input for receiving binary signals resulting from opening and closing one of a plurality of input switches connectable with a DC power source and located within the process, and an output for sending a first binary signal when no input signal is received and a second binary signal when an input signal is received, a system for detecting faults in the priority interrupt isolation circuits comprising: means for isolating the input of each of said plurality of priority interrupt circuits from the binary signals transmitted through the plurality of input switChes; means for reading the outputs of the plurality of priority interrupt circuits, wherein it can be determined that a priority interrupt circuit is operable if a second binary signal is read; means for providing a test signal to each input of the plurality of priority interrupt circuits; means for reading each of the outputs of the plurality of priority interrupt circuits wherein it can be determined that a priority interrupt circuit is inoperable if a first binary signal is read.

Claim 22

A system as in claim 18 wherein said test signal providing means comprises: a normally open test switch having first and second terminals, the first terminal being connectable with a direct current voltage source; a plurality of diodes corresponding to the number of priority interrupt circuits, each having an anode terminal connected to the second terminal of said test switch and each having a cathode terminal connected to the input of one of said plurality of priority interrupt circuits, such that whenever said test switch is closed a signal is provided to the inputs of each of the priority interrupt circuits.

Claim 23

A system as in claim 19 including means for determining the integrity of the test signal providing means comprising a test signal input interrupt circuit, having an input connected with the second terminal of said test switch and an output which provides a first binary output signal whenever there is an absence of a signal at the input and a second binary output signal when there is a signal at the input, such that if said second binary ''''ONE'''' signal is provided at the output of said test signal input interrupt circuit when said test switch is ordered open it is indicative that one of the elements of said test signal providing means is inoperable.