Stored program system

Claim 2

A stored program data processing system for use in control of the operation of load equipment, such as a telephone system, comprising a memory providing a plurality of data storage areas for storing data including programs of instruction made up of plural cycles of steps, logic control means operatively connected to said memory for manipulating and logically operating upon data necessary to control of said load equipment in response to said programs of instructions stored in said memory, peripheral control means connected between said logic control means and said load equipment for providing to said logic control means electrical indications relating to the instantaneous operating condition of said load equipment and for providing from said logic control means to said load equipment control signals capable of effecting the required control of said equipment, instruction translating means operatively connected to said logic control means for providing actuation of said logic control Means in accordance with the cycles of steps of respective instructions derived from the programs stored in said memory, and cycle control means connected to said instruction translating means and said logic control means for effecting sequential actuation thereof to provide control for each respective cycle on an instruction in a prescribed order.

Claim 3

A stored program data processing system as defined in claim 1 wherein said logic control means includes a plurality of data storage registers, an arithmetic and logic unit selectively connected in parallel with said storage registers for effecting transfer and arithmetic manipulation of data, and switch means for permitting flow of data from a given one of said storage registers to another one of said storage registers through said arithmetic and logic unit.

Claim 4

A stored program data processing system as defined in claim 2 wherein said plurality of data storage registers include address and data storage registers connected to said memory and an instruction register connected at its output to said instruction translating means, said address and data storage registers having outputs connected to an input of said arithmetic and logic unit for transferring data therethrough to an input of said instruction register.

Claim 5

A stored program data processing system as defined in claim 3 wherein said plurality of data storage registers further includes a pair of addressable registers connected in parallel with each other and with said arithmetic and logic unit.

Claim 6

A stored program data processing system as defined in claim 3 wherein said plurality of data storage registers further includes an instruction address register connected in parallel with said arithmetic and logic unit for storing the address of the storage location of an instruction being performed by the system.

Claim 7

A stored program data processing system as defined in claim 3 wherein said plurality of data storage registers further includes address scan and data transfer registers for transferring addresses and data to said peripheral control means and for receiving data from said peripheral control means.

Claim 8

A stored program data processing system as defined in claim 2 wherein said logic control means further includes a controlled number generator connected to the input of said arithmetic and logic unit.

Claim 9

A stored program data processing system as defined in claim 2 wherein said arithmetic and logic unit has first and second inputs, a data output and a test output, a full adder and a full subtracter connected between said first and second inputs and said data output, and control inputs for selective application of data to said full adder or said full subtractor for processing.

Claim 10

A stored program data processing system as defined in claim 8 wherein said arithmetic and logic unit further includes a carry flip-flop having outputs connected to said full adder and said full subtracter and inputs connected to said control inputs and to outputs of said full adder and said full subtracter for providing products and complements of products of applied data.

Claim 11

A stored program data processing system as defined in claim 9 wherein said arithmetic and logic unit further includes first gating means for selectively effecting a direct transfer of data from said first or second input to said data output and second gating means for effecting a complementing of said data on a selective basis.

Claim 12

A stored program data processing system as defined in claim 2 wherein said arithmetic and logic unit includes at least one input and a test output, first and second test flip-flops, an exclusive OR gate having a pair of inputs connected to the outputs of said test flip-flops and an output connected to said test output, and gating means for selectively applying data and control signals to control the operation of said test flip-flops.

Claim 13

A stored program data processing system as defined in claim 11 wherein said gating means includes a first gate for setting said one test flip-flop and a second gate for selectively connecting said first input to said second test flip-flop upon receipt of a predetermined data impulse, which if a ''''1'''' will set said second test flip-flop and block the output of said exclusive OR gate. impulse

Claim 14

A stored program data processing system as defined in claim 11 wherein said gating means includes a first gate connecting said first input to the input of said first test flip-flop to set said flip-flop upon receipt of a ''''1,'''' and a second gate for selectively connecting said first input to said second test flip-flop upon receipt of a pre-determined data impulse, such that if said first flip-flop is set and said predetermined data impulse is a ''''1'''' said second test flip-flop will be set and the output of said exclusive OR gate will be blocked.

Claim 15

A stored program data processing system as defined in claim 1 wherein said instruction translating means includes instruction decoder means connected to said logic control means for providing an instruction enable output in response to receipt of an instruction signal stored in said memory and instruction cycle decoder means connected to said instruction decoder means for providing a cycle enable output for each cycle of the instruction represented by a received instruction enable output, and encoder means responsive to each cycle enable output for controlling actuation of said logic control means.

Claim 16

A stored program data processing system as defined in claim 14 wherein said instruction decoder means includes a plurality of inputs each receiving a respective bit of a bit combination representing an instruction and a plurality of outputs each representing a respective individual instruction forming said stored programs.

Claim 17

A stored program data processing system as defined in claim 14 wherein said cycle control means includes machine cycle sequencer means connected to said instruction cycle decoder means for sequentially connecting said cycle enable outputs to said encoder means in said prescribed order.

Claim 18

A stored program data processing system as defined in claim 16 wherein said instruction cycle decoder means includes an instruction decoder matrix having first coordinate lines connected to the outputs of said instruction decoder means and second coordinate lines connected to said machine cycle sequencer means such that respective cross-points of the matrix relating to a given first coordinate are sequentially enabled.

Claim 19

A stored program data processing system as defined in claim 16 wherein said machine cycle sequencer means includes at least two sequencer sections, one of said sequencer sections being connected to said instruction cycle decoder means and the other sequencer section being connected to said encoder means.

Claim 20

A stored program data processing system as defined in claim 18, wherein said instruction translation means further includes pre-processing cycle decoder means providing fixed pre-processing cycle control signals, said machine cycle sequencer means including a third sequencer section connected to said pre-processing cycle decoder for sequentially, enabling application of said pre-processing cycle control signals to said encoder means.

Claim 21

A stored program data processing system as defined in claim 19 wherein said third sequencer section and said two sequencer sections are operated in sequence.

Claim 22

A stored program data processing system as defined in claim 16 wherein said machine cycle sequencer means includes at least one sequencer section comprising at least first and second flip-flops each having a set input, a reset input, a clock input, and an enable input, a source of clock pulses connected to said clock input of each flip-flop, and gating means connected to said first and second flip-flops for actuating said first flip-flop, then said second flip-flop, the both flip-flops in response to successively received clock pulses.

Claim 23

A stored program data processiNg system as defined in claim 21 wherein said sequencer section has a single input connected to the set input of said first flip-flop, said reset input of said second flip-flop being connected to said set input of said first flip-flop.

Claim 24

A stored program data processing system as defined in claim 22 wherein said first and second flip-flops each include a set output and a reset output, and said gating means includes an AND gate having a first input connected to the reset output of said first flip-flop, a second input connected to the set input of said second flip-flop and an output connected to the enable input of said first flip-flop.

Claim 25

A stored program data processing system as defined in claim 23 wherein said gating means further includes an exclusive OR gate having a first input connected to the set output of said first flip-flop, a second input connected to the set input of said second flip-flop and an output connected to the enable input of said second flip-flop.

Claim 26

A stored program data processing system as defined in claim 21 wherein said gating means includes means for automatically shutting off said sequencer section after completion of a sequence of operation.

Claim 27

A stored program data processing system as defined in claim 21 wherein said sequencer section includes at least three flip-flops, said gating means being connected to said three flip-flops for actuation thereof in sequential order, each flip-flop having two enable inputs.

Claim 28

A stored program data processing system as defined in claim 26 wherein said gating means includes a first AND gate and a second AND gate for each flip-flop, the outputs of said AND gates being connected to the respective enable inputs of the associated flip-flop and the inputs thereof being connected respectively to the set output of one of the other two flip-flops and to the reset output of the remaining two flip-flops.

Claim 29

A stored program data processing system as defined in claim 21 wherein said machine cycle sequencer means includes at least two of said sequencer sections, each sequencer section including an individual input connected to the set input of the first flip-flop of the section, and further including additional gating means for connecting the input of each sequencer section to the reset inputs of all of the flip-flops in the other sequencer section.

Claim 30

A stored program data processing system as defined in claim 28 wherein said machine cycle sequencer means further includes first indicator means connected to an output of each sequencer section to provide an indication that no sequencer section is actuated.

Claim 31

A stored program data processing system as defined in claim 28 wherein said machine cycle sequencer means further includes second indicator means connected to an output of each of said sequencer sections to provide an indication that more than one sequencer section is actuated at the same time.

Claim 32

A stored program data processing system as defined in claim 1 wherein said cycle control means includes a plurality of sequencers for controlling the transfer of data within the system.

Claim 33

A stored program data processing system as defined in claim 31 wherein said cycle control means includes a bit sequencer connected to said logic control means for effecting the bit-by-bit transfer of data therein.

Claim 34

A stored program data processing system as defined in claim 32 wherein said cycle control means includes a peripheral sequencer connected to said peripheral control means for effecting transfer of data between said load equipment and said logic control means via said peripheral control means.

Claim 35

A stored program data processing system as defined in claim 33 wherein said cycle control means includes a memory sequencer connected to said memory for effecting transfer of data to and from said memory.

Claim 36

A stored program data processing system as defined in claim 34 wherein said cycle control means includes central control means for sequentially enabling said plurality of seQuencers in a prescribed order of operation.

Claim 37

A stored program data processing system as defined in claim 16 wherein said cycle control means further includes central control means for controlling operation of said machine cycle sequencer means to reset and increment said machine cycle.

Claim 38

A stored program data processing system as defined in claim 36 wherein said central control means includes a central control enable flip-flop providing an enable output to said machine cycle sequencer means to start a new cycle and a machine cycle increment flip-flop providing an increment output to said machine cycle sequencer means.

Claim 39

A stored program data processing system as defined in claim 37 wherein said central control means further includes a cycle flip-flop and a reset cycle flip-flop, said central control means having a reset input connected to said reset cycle flip-flop which is connected to said cycle flip-flop and said central control enable flip-flop so that said cycle flip-flop is not reset until the end of a cycle of operation, said cycle flip-flop providing for operation of said central control means.

Claim 40

A stored program data processing system as defined in claim 38 wherein said cycle control means includes a plurality of sequencers for controlling the transfer of data within the system.

Claim 41

A stored program data processing system as defined in claim 39 wherein said central control means includes an input from said plurality of sequencers connected to reset said central control enable flip-flop.

Claim 42

A stored program data processing system as defined in claim 40 wherein said central control means includes an increment enable flip-flop enabled upon actuation of one of said plurality of sequencers, said increment enable flip-flop being connected to said machine cycle increment flip-flop so as to set the latter flip-flop upon being reset by de-actuation of said one sequencer.

Claim 43

A stored program data processing system as defined in claim 41 wherein said central control means includes a keep running flip-flop connected to said central control enable flip-flop for setting said machine cycle increment flip-flop in absence of actuation of one of said plurality of sequencers.

Claim 44

A stored program data processing system as defined in claim 1 wherein said load equipment includes a telephone system comprising a plurality of subscriber circuits, a plurality of terminating circuits in the form of junctors and trunks, and a multi-stage switching network for interconnecting said subscriber circuits and said terminating circuits in accordance with subscriber requests.

Claim 45

A stored program data processing system as defined in claim 43 wherein said peripheral control means includes line scanner and marker means connected to said subscriber circuits for scanning said subscriber circuits for requests for service and marking those subscriber circuits in which requests are detected.

Claim 46

A stored program data processing system as defined in claim 44 wherein said line scanner and marker means includes a binary counter having a start input, a stop input connected to each line circuit and an output, line number decoder means connected to the output of said binary counter for sequentially applying a signal to each line circuit those line circuits requesting service connecting said signal to the stop input of said binary counter.

Claim 47

A stored program data processing system as defined in claim 45 wherein the line from said line circuits to the stop input of said binary counter is also connected to the input of a data gate connected to said logic control means.

Claim 48

A stored program data processing system as defined in claim 43 wherein said peripheral control means includes a terminating circuit mark and release means connected to said terminating circuits for marking and releasing thereof.

Claim 49

A stored program data processing system as defined in claim 47 wherein said terminating circuit mark and release means includes mark register means for receiving aNd storing the identity of a terminating circuit including a switching link from said logic control means, first decoder means for decoding the identity of the terminating circuit and second decoding means for decoding the identity of the switching link, and mark timing means for enabling the output of said second decoding means prior to enabling the output of said first decoding means.

Claim 50

A stored program data processing system as defined in claim 48 wherein said terminating circuit mark and release means further includes release register means for storing the identity of a terminating circuit to be released, a release decoder connected between said release register and said terminating circuit for releasing a given terminating circuit and release timing means for de-actuating said release decoder after a prescribed time period sufficient to release a terminating circuit.

Claim 51

A stored program data processing system as defined in claim 43 wherein said peripheral control means includes a tone sequencer means connected to said terminating circuits for applying dial tone thereto.

Claim 52

A stored program data processing system as defined in claim 50 wherein said tone sequencer means includes register means for receiving and storing the identity of a terminating circuit including a tone code from said logic control means, first decoder means for decoding the identity of the terminating circuit and second decoding means for decoding the identity of the tone code, and timing means for enabling the output of said first and second decoding means.

Claim 53

A stored program data processing system as defined in claim 51 wherein said tone sequencer means further includes release register means for storing the identity of a terminating circuit from which dial tone is to be released, a release decoder connected between said release register and said terminating circuit for releasing a given terminating circuit and release timing means for de-actuating said release decoder after a prescribed time period sufficient to release dial tone from a terminating circuit.

Claim 54

A stored program data processing system for use in control of the operation of load equipment including a telephone system providing a plurality of subscriber circuits, a plurality of terminating circuits in the form of junctors and trunks, and a multi-stage switching network for interconnecting said subscriber circuits and said terminating circuits in accordance with subscriber requests, comprising a memory providing a plurality of data storage areas for storing data including programs of instruction made up of plural cycles of steps, logic control means operatively connected to said memory for manipulating and logically operating upon data necessary to control of said load equipment in response to said programs of instructions stored in said memory, peripheral control means connected between said logic control means and said load equipment for providing to said logic control means electrical indications relating to the instantaneous operating condition of said load equipment and for providing from said logic control means to said load equipment control signals capable of effecting the required control of said equipment, instruction translating means operatively connected to said logic control means for providing actuation of said logic control means in accordance with the cycles of steps of respective instructions derived from the programs stored in said memory, and cycle control means connected to said instruction translating means and said logic control means for effecting sequential actuation thereof to provide control for each respective cycle on an instruction in a prescribed order, said logic control means including a plurality of data storage registers, an arithmetic and logic unit selectively connected in parallel with said storage registers for effecting transfer and arithmetic manipulation of data, and switch means for permitting flow of data from a given one of said storage rEgisters to another one of said storage registers through said arithmetic and logic unit.

Claim 55

A stored program data processing system for use in control of the operation of load equipment including a telephone system providing a plurality of subscriber circuits, a plurality of terminating circuits in the form of junctors and trunks, and a multi-stage switching network for interconnecting said subscriber circuits and said terminating circuits in accordance with subscriber requests, comprising a memory providing a plurality of data storage areas for storing data including programs of instruction made up of plural cycles of steps, logic control means operatively connected to said memory for manipulating and logically operating upon data necessary to control of said load equipment in response to said programs of instructions stored in said memory, peripheral control means connected between said logic control means and said load equipment for providing to said logic control means electrical indications relating to the instantaneous operating condition of said load equipment and for providing from said logic control means to said load equipment control signals capable of effecting the required control of said equipment, instruction translating means operatively connected to said logic control means for providing actuation of said logic control means in accordance with the cycles of steps of respective instructions derived from the programs stored in said memory, and cycle control means connected to said instruction translating means and said logic control means for effecting sequential actuation thereof to provide control for each respective cycle on an instruction in a prescribed order, said logic control means including a plurality of data storage registers, an arithmetic and logic unit selectively connected in parallel with said storage registers for effecting transfer and arithmetic manipulation of data, and switch means for permitting flow of data from a given one of said storage rEgisters to another one of said storage registers through said arithmetic and logic unit.

Claim 56

A stored program data processing system as defined in claim 53 wherein said peripheral control means includes line scanner and marker means connected to said subscriber circuits for scanning said line circuits for requests for service and marking those subscriber circuits in which requests are detected.

Claim 57

A stored program data processing system as defined in claim 53 wherein said peripheral control means includes a terminating circuit mark and release means connected to said terminating circuits for marking and releasing thereof.

Claim 58

A stored program data processing system as defined in claim 53 wherein said peripheral control means includes a tone sequencer means connected to said terminating circuits for applying dial tone thereto.

Claim 59

A stored program data processing system as defined in claim 53 wherein said plurality of data storage registers include address and data storage registers connected to said memory and an instruction register connected at its output to said instruction translating means, said address and data storage registers having outputs connected to an input of said arithmetic and logic unit for transferring data therethrough to an input of said instruction register.

Claim 60

A stored program data processing system as defined in claim 57 wherein said plurality of data storage registers further includes an instruction address register connected in parallel with said arithmetic and logic unit for storing the address of the storage location of an instruction being performed by the system.

Claim 61

A stored program data processing system as defined in claim 57 wherein said plurality of data storage registers further includes address, scan and data transfer registers for transferring addresses and data to said peripheral control means and for receiving data from said peripheral control means.

Claim 62

A stored program data processing system as defined in claim 53 wherein said arithmetic and logic unit includes at least one input and a test output, first and second test flip-flops, an exclusive OR gate having a pair of inputs connected to the outputs of said test flip-flops and an output connected to said test output, and gating means for selectively applying data and control signals to control the operation of said test flip-flops.

Claim 63

A stored program data processing system as defined in claim 60 wherein said gating means includes a first gate for setting said first test flip-flop and a second gate for selectively connecting said one input to said second test flip-flop upon receipt of a predetermined data impulse, which if a ''''1'''' will set said second test flip-flop and block the output of said exclusive OR gate.

Claim 64

A stored program data processing system as defined in claim 60 wherein said gating means includes a first gate connecting said one input to the input of said first test flip-flop to set said flip-flop upon receipt of a ''''1,'''' and a second gate for selectively connecting said one input to said second test flip-flop upon receipt of a predetermined data impulse, such that if said first flip-flop is set and said predetermined data impulse is a ''''1'''' said second test flip-flop will be set and the output of said exclusive OR gate will be blocked.

Claim 65

A stored program data processing system as defined in claim 53 wherein said cycle control means includes a plurality of sequencers for controlling the transfer of data within the system and central control means for sequentially enabling said plurality of sequencers in a prescribed order of operation.

Claim 66

A stored program data processing system as defined in claim 63 wherein said instruction translating means includes instruction decoder means connected to said logic control means for providing an instruction enable output in response to receipt of an instruction signal stored in said memory and instruction cycle decoder means connected to said instruction Decoder means for providing a cycle enable output for each cycle of the instruction represented by a received instruction enable output, and encoder means responsive to each cycle enable output for controlling actuation of said logic control means.

Claim 67

A stored program data processing system as defined in claim 64 wherein said instruction decoder means includes a plurality of inputs each receiving a respective bit of a bit combination representing an instruction and a plurality of outputs each representing a respective individual instruction forming said stored programs.

Claim 68

A stored program data processing system as defined in claim 65 wherein said cycle control means includes machine cycle sequencer means connected to said instruction cycle decoder means for sequentially connecting said cycle enable outputs to said encoder means in said prescribed order.

Claim 69

A stored program data processing system as defined in claim 66 wherein said cycle control means further includes central control means for controlling operation of said machine cycle sequencer means to reset and increment said machine cycle sequencer means.

Claim 70

A stored program data processing system as defined in claim 67 wherein said central control means includes a central control enable flip-flop providing an enable output to said machine cycle sequencer means to start a new cycle and a machine cycle increment flip-flop providing an increment output to said machine cycle sequencer means.

Claim 71

A stored program data processing system as defined in claim 66 wherein said instruction cycle decoder means includes an instruction decoder matrix having first coordinate lines connected to the outputs of said instruction decoder means and second coordinate lines connected to said machine cycle sequencer means such that respective cross-points of the matrix relating to a given first coordinate are sequentially enabled.

Claim 72

A stored program data processing system as defined in claim 69 wherein said machine cycle sequencer means includes at least two sequencer sections, one of said sequencer sections being connected to said instruction cycle decoder means and the other sequencer section being connected to said encoder means.

Claim 73

A stored program data processing system as defined in claim 70, wherein said instruction translation means further includes pre-processing cycle decoder means providing fixed pre-processing cycle control signals, said machine cycle sequencer means including a third sequencer section connected to said pre-processing cycle decoder for sequentially enabling application of said pre-processing cycle control signals to said encoder means.

Claim 74

A stored program data processing system as defined in claim 71 wherein said third sequencer section and said two sequencer sections are operated in sequence.

Claim 75

A stored program data processing system as defined in claim 66 wherein said machine cycle sequencer means includes at least one sequencer section comprising at least first and second flip-flops each having a set input, a reset input, a clock input and an enable input, a source of clock pulses connected to said clock input of each flip-flop, and gating means connected to said first and second flip-flops for actuating said first flip-flop, then said second flip-flop, then both flip-flops in response to successively received clock pulses.

Claim 76

A stored program data processing system as defined in claim 73 wherein said sequencer section has a single input connected to the set input of said first flip-flop, said reset input of said second flip-flop being connected to said set input of said first flip-flop.

Claim 77

A stored program data processing system as defined in claim 74 wherein said first and second flip-flops each include a set output and a reset output, and said gating means includes an AND gate having a first input connected to the reset output of said first flip-flop, a second input connected to the set input of said second flip-flop and an output connected to the enable input of said first flip-flop.

Claim 78

A stored program data processing system as defined in claim 75 wherein said gating means further includes an exclusive OR gate having a first input connected to the set output of said first flip-flop, a second input connected to the set input of said second flip-flop and an output connected to the enable input of said second flip-flop.

Claim 79

A stored program data processing system as defined in claim 75 wherein said gating means includes means for automatically shutting off said sequencer section after completion of a sequence of operation.

Claim 80

A stored program data processing system as defined in claim 73 wherein said sequencer section includes at least three flip-flops, said gating means being connected to said three flip-flops for actuation thereof in sequential order, each flip-flop having two enable inputs.

Claim 81

A stored program data processing system as defined in claim 78 wherein said gating means includes a first AND gate and a second AND gate for each flip-flop, the outputs of said AND gates being connected to the respective enable inputs of the associated flip-flop and the inputs thereof being connected respectively to the set output of one of the other two flip-flops and to the reset output of the remaining two flip-flops.

Claim 82

A stored program data processing system as defined in claim 73 wherein said machine cycle sequencer means includes at least two of said sequencer sections, each sequencer section including an individual input connected to the set input of the first flip-flop of the section, and further including additional gating means for connecting the input of each sequencer section to the reset inputs of all of the flip-flops in the other sequencer section.

Claim 83

A stored program data processing system as defined in claim 80 wherein said machine cycle sequencer means further includes first indicator means connected to an output of each sequencer section to provide an indication that no sequencer section is actuated.

Claim 84

A stored program data processing system as defined in claim 81 wherein said machine cycle sequencer means further includes second indicator means connected to an output of each of said sequencer sections to provide an indication that more than one sequencer section is actuated at the same time.