In-circuit digital tester

Claim 2

Apparatus for the in-circuit testing of the electrical properties of components of a circuit, comprising: (a) a central processing unit for controlling the tests to be performed and for interpreting the results of said tests; (b) electrical test pins, contactable with electrical nodes in said circuit; (c) sets of selectable switches, one set associated with each of said test pins, for connecting each of said test pins to at least one of a plurality of signal lines associated with each said pin, said signal lines including a response signal line; (d) a plurality of digital test-signal generators, each of said generators being associated with one of said test pins, for generating at least one digital test signal from a set of test signals, the output line from each of said generators comprising one of the plurality of signal lines for the test pin associated with said generator; (e) switch-selecting means responsive to the central processor, for selecting at least one of said selectable switches, to connect selected ones of said test pins to their associated plurality of signal lines, thereby to connect one of said plurality of digital test-signal generators to one of the nodes of the circuit, and to connect a node of the circuit to the response signal line; (f) a test controller responsive to the central processor, for generating a test cycle wherein said digital test-signal generators supply test signals to said circuit, thereby to cause the circuit to produce a response signal on said response signal line; and (g) a functional tester responsive to the central processor, for testing the signal on said response signal line, to determine electrical properties of said circuit.

Claim 3

The apparatus in accordance with claim 1 wherein said electrical test pins comprise a bed of nails fixture.

Claim 4

The apparatus of claim 1, wherein the plurality of selectable switches in each of said sets of selectable switches includes four selectable switches.

Claim 5

The apparatus of claim 1, wherein said selectable switches are reed switches.

Claim 6

The apparatus of claim 1, wherein said set of test signals includes a set of Gray Code test signals.

Claim 7

The apparatus of claim 5 wherein, the set of Gray Code test signals comprises fourteen digital test signals.

Claim 8

The apparatus of claim 1, wherein each of said digital test-signal generators includes: (a) a memory address generator for generating a sequence of memory addresses during said test cycle; (b) a first memory responsive to said address generator, for outputting a logic signal to select a digital test signal, said memory having a specified storage location for each digital test signal, said logic signal enabling a transition in said selected test signal; (c) a second memory responsive to said address generator, for outputting a logic signal to enable and to disable the generation of said selected test signal; (d) a synchronization signal generator responsive to said memory address generator for generating synchronization signals; and (e) a driver responsive to the output from said first and second memories, and to said synchronization signals, for generating the selected digital test signal and for applying said selected digital test signal to an electrical node of said circuit.

Claim 9

The apparatus of claim 7, wherein said sequence of memory addresses comprises the ordered sequential addresses of each of the addressable storage locations of said first memory and said second memory, each address in said sequence enabling a transition in said digital test signal specified by that address.

Claim 10

The apparatus of claim 8, wherein said first memory further comprises a memory location for storing an initialization bit, and another memory location for storing a preset bit, said initialization and preset bits specifying one of a plurality of possible beginning sequences for each of said digital test signals.

Claim 11

The apparatus of claim 7, wherein said synchronization signal generator includes: (a) means for generating a first synchronization signal having a transition for each address of said address generator; and (b) means for generating a second synchronization signal having a transition, (i) on the first occurrence of each address in said sequence of memory addresses, or (ii) on each occurrence of any or all addresses in said sequence of memory addresses.

Claim 12

The apparatus of claim 7, wherein said digital test signal generator further comprises means responsive to said processor for addressing and storing in said first and second memories digital-test-signal-generating data prior to the generation of said test cycle.

Claim 13

The apparatus of claim 1, wherein said test controller includes: (a) an internal oscillator; (b) a threshold voltage generator responsive to said processor for generating a negative offset voltage to offset the voltages produced by externally generated signals inputted to the testing apparatus, the external signals including an external clock signal; (c) a system clock generator responsive to the external clock signal, said processor, said oscillator and said threshold voltage generator, for generating a system clock, said system clock being derived from said internal oscillator or from the external clock; (d) a command decoder responsive to said processor, for generating system commands to control the functions of said tester; (e) a listen enable generator responsive to said processor and said digital test-signal generators, for controlling the length of said test cycle, and for generating a listen enable signal to enable said functional tester to perform functional tests on said response signal during the generation of said listen enable signal; and (f) a start test cycle generator responsive to said clock, said listen enable generator, and said command decoder, for starting and stopping said test cycle.

Claim 14

The apparatus of claim 12, wherein said system clock generator includes a divide-by-N counter.

Claim 15

The device of claim 12, wherein said threshold voltage generator is a digital-to-analog converter.

Claim 16

The apparatus of claim 1, wherein said functional tester includes a cyclic redundancy check function tester for generating a digital code representative of the length and character of the serial digital data stream of said response signal, said code representing the signature of said response signal.

Claim 17

A testing apparatus adapted for use with a computer for the in-circuit testing of a circuit having electrical nodes, comprising: (a) a node-connecting means associated with each of a selected ones of said nodes and responsive to the computer, each selected node having associated therewith signal lines including a response signal line, for connecting each of the selected nodes to its associated signal lines, one of said selected nodes being connected to the response signal line; (b) a digital test-signal generator associated with each said node-connecting means, for generating at least one digital test signal from a set of digital test signals, the output line from each said generator comprising one of the associated signal lines for the node associated with said generator; (c) a controller responsive to the computer, for generating a test cycle in which selected ones of said test signals are applied through said associated node-connecting means to selected ones of said selected nodes, said circuit generating a signal on said response signal line in response to said applied test signals; and (d) a functional tester connected to the response signal line and responsive to the computer, for performing functional tests on said response signal to determine electrical properties of said circuit.

Claim 18

A testing apparatus adapted for use with a computer for the in-circuit testing of a circuit having electrical nodes, comprising: (a) a node-connecting means associated with each of a selected ones of said nodes and responsive to the computer, each selected node having associated therewith signal lines including a response signal line, for connecting each of the selected nodes to its associated signal lines, one of said selected nodes being connected to the response signal line; (b) a digital test-signal generator associated with each said node-connecting means, for generating at least one digital test signal from a set of digital test signals, the output line from each said generator comprising one of the associated signal lines for the node associated with said generator; (c) a controller responsive to the computer, for generating a test cycle in which selected ones of said test signals are applied through said associated node-connecting means to selected ones of said selected nodes, said circuit generating a signal on said response signal line in response to said applied test signals; and (d) a functional tester connected to the response signal line and responsive to the computer, for performing functional tests on said response signal to determine electrical properties of said circuit.

Claim 19

The apparatus of claim 16, wherein each said node-connecting means includes: (a) a test pin contactable with an associated selected electrical node of said circuit; and (b) a set of selectable switches connected to each of said test pins, for connecting each test pin to one of its associated signal lines; and (c) switch selecting means responsive to the computer, for selecting at least one of said selectable switches, (i) to connect one of said plurality of digital test-signal generators to one of the nodes of the circuit, and (ii) to connect a node of the circuit to the response signal line.

Claim 20

The apparatus of claim 17, wherein each said set of selectable switches includes a switch for connecting the output from one of said associated digital test-signal generators to its associated test pin.

Claim 21

The apparatus in accordance with claim 16, wherein said functional tester includes: (a) an analog-to-digital converter; (b) a counter for counting (i) the number of cycles in a clock signal that occurred when said response test signal is at a logic high state, or (ii) the number of pulses in said response test signal that occur in said test cycle; and (c) a cyclic redundancy check generator, for generating a digital code for the serial bit stream of said response test signal, said code representing the signature of said signal.

Claim 22

The apparatus of claim 16, wherein said controller includes: (a) a system clock generator responsive to said computer for generating a master system clock for said tester; (b) a command decoder responsive to said computer for generating control signals to control the functions of said tester; (c) a listen enable generator responsive to said computer and said digital test-signal generators, for generating a listen enable signal, to enable said functional tester to perform functional tests on said response signal during the generation of said listen enable signal, and for controlling the length of said test cycle; and (d) a start test cycle generator responsive to said system clock, said command decoder and said listen enable generator, for starting the stoping said test cycle.

Claim 23

Apparatus adapted for use with a central processor for the in-circuit testing of the electrical properties of a circuit under test, said apparatus having a response signal line for monitoring the response signal from the circuit under test, the apparatus comprising: (a) electrical test pins, contactable with electrical nodes in said circuit; (b) a selectable switch associated with each test pin, for selectively connecting the associated said test pin to the response signal line; (c) a plurality of digital test-signal generators, one associated with each of said test pins, for generating at least one digital test signal from a set of test signals, the output line from each said generator adapted for connection to its associated test pin; (d) switch-selecting means responsive to the central processor, for selecting one said selectable switch to connect a node of said circuit to said response signal line; and (e) a test controller responsive to the central processor, for generating a test cycle wherein selected ones of said digital test-signal generators supply test signals to said circuit, thereby to cause the circuit under test to produce a response signal on said response signal line.

Claim 24

Apparatus adapted for use with a central processor for the in-circuit testing of the electrical properties of a circuit under test, said apparatus having a response signal line for monitoring the response signal from the circuit under test, the apparatus comprising: (a) electrical test pins, contactable with electrical nodes in said circuit; (b) a selectable switch associated with each test pin, for selectively connecting the associated said test pin to the response signal line; (c) a plurality of digital test-signal generators, one associated with each of said test pins, for generating at least one digital test signal from a set of test signals, the output line from each said generator adapted for connection to its associated test pin; (d) switch-selecting means responsive to the central processor, for selecting one said selectable switch to connect a node of said circuit to said response signal line; and (e) a test controller responsive to the central processor, for generating a test cycle wherein selected ones of said digital test-signal generators supply test signals to said circuit, thereby to cause the circuit under test to produce a response signal on said response signal line.

Claim 25

The apparatus in accordance with claim 21 further comprising a functional tester connected to the response signal line and responsive to the central processor, for testing the signal on the response signal line, to determine electrical properties of the circuit.

Claim 26

The apparatus in accordance with claim 21 wherein said electrical test pins comprise a bed of nails fixture.

Claim 27

The apparatus of claim 21, wherein said selectable switch is a reed switch.

Claim 28

The apparatus of claim 21, wherein the set of test signals includes a set of Gray Code test signals.

Claim 29

The apparatus of claim 25, wherein the set of Gray Code test signals comprises fourteen digital test signals.

Claim 30

The apparatus of claim 21, wherein each of said digital test-signal generators includes: (a) a memory address generator for generating a sequence of memory addresses during said test cycle; (b) a first memory responsive to said address generator, for outputting a logic signal to select a digital test signal , said memory having a specified storage location for each digital test signal, said logic signal enabling a transition in said selected test signal; (c) a second memory responsive to said address generator, for outputting a logic signal to enable and to disable the generation of said selected test signal; (d) a synchronization signal generator responsive to said memory address generator for generating synchronization signals; and (e) a driver responsive to the output from said first and second memories, and to said synchronization signals, for generating the selected digital test signal and for applying said selected digital test signal to an electrical node of said circuit.

Claim 31

The apparatus of claim 27, wherein said sequence of memory addresses comprises the ordered sequential addresses of each of the addressable storage locations of said first memory and said second memory, each address in said sequence enabling a transition in said digital test signal specified by that address.

Claim 32

The apparatus of claim 28, wherein said first memory further comprises a memory location for storing an initialization bit, and another memory location for storing a preset bit, said initialization and preset bits specifying one of a plurality of possible beginning sequence for each of said digital test signals.

Claim 33

The apparatus of claim 27, wherein said synchronization signal generator includes: (a) means for generating a first synchronization signal having a transition for each address of said address generator; and (b) means for generating a second synchronization signal having a transition, (i) on the first occurrence of each address in said sequence of memory addresses, or (ii) on each occurrence of any or all addresses in said sequence of memory addresses.

Claim 34

The apparatus of claim 27, wherein said digital test signal generator futher comprises means responsive to said processor for addressing and storing in said first and second memories digital-test-signal-generating data prior to the generation of said test cycle.

Claim 35

The apparatus of claim 22, wherein said test controller includes: (a) an internal oscillator; (b) a threshold voltage generator responsive to said processor for generating a negative offset voltage to offset the voltages produced by externally generated signals inputted to the testing apparatus, said external signals including an external clock signal; (c) a system clock generator responsive to the external clock signal, said processor, said oscillator and said threshold voltage generator, for generating a system clock, said system clock being derived from said internal oscillator or from the external clock; (d) a command decoder responsive to said processor, for generating system commands to control the functions of said tester; (e) a listen enable generator responsive to said processor and said digital test-signal generator, for controlling the length of said test cycle, and for generating a listen enable signal to enable said functional tester to perform functional tests on said response signal during the generation of said listen enable signal; and (f) a start test cycle generator responsive to said listen enable generator, for starting and stopping said test cycle.

Claim 36

The apparatus of claim 32, wherein said system clock generator includes a divide-by-N counter.

Claim 37

The device of claim 32, wherein said threshold voltage generator is a digital-to-analog converter.

Claim 38

The apparatus in accordance with claim 22, wherein said functional tester includes: (a) an analog-to-digital converter; (b) a counter for counting (i) the number of cycles in a clock signal that occurred when said response signal is at a logic high state, or (ii) the number of pulses in said response signal that occur in said test cycle; and (c) a cyclic redundancy check generator, for generating a digital code from the serial bit stream of said response signal, said code representing the signature of said signal.

Claim 41

The apparatus according to claim 36 further comprising a functional tester responsive to the central processor, for testing the signal on said response signal line, to determine electrical properties of the components of said circuit.

Claim 42

The apparatus in accordance with claim 36 wherein said electrical test pins comprise a bed of nails fixture.

Claim 43

The apparatus of claim 36, wherein each of said sets of selectable switches includes four selectable switches.

Claim 44

The apparatus of claim 36, wherein said selectable switches are reed switches.

Claim 45

The apparatus of claim 36, wherein said set of test signals includes a set of Gray Code test signals.

Claim 46

The apparatus of claim 41 wherein, the set of Gray Code test signals comprises fourteen digital test signals.

Claim 47

The apparatus of claim 36, wherein each of said digital test-signal generators includes: (a) a memory address generator for generating a sequence of memory addresses during said test cycle; (b) a first memory responsive to said address generator, for outputting a logic signal to select a digital test signal, said memory having a specified storage location for each digital test signal, said logic signal enabling a transition in said selected test signal; (c) a second memory responsive to said address generator, for outputting a logic signal to enable and to disable the generation of said selected test signal; (d) a synchronization signal generator responsive to said memory address generator for generating synchronization signals; and (e) a driver responsive to the output from said first and second memories, and to said synchronization signals, for generating the selected digital test signal and for applying said selected digital test signal to an electrical node of said circuit.

Claim 48

The apparatus of claim 43, wherein said sequence of memory addresses comprises the ordered sequential addresses of each of the addressable storage locations of said first memory and said second memory, each address in said sequence enabling a transition in said digital test signal specified by that address.

Claim 49

The apparatus of claim 44, wherein said first memory further comprises a memory location for storing an initialization bit, and another memory location for storing a preset bit, said initialization and preset bits specifying one of a plurality of possible beginning sequences for each of said digital test signals.

Claim 50

The apparatus of claim 43, wherein said synchronization signal generator includes: (a) means for generating a first synchronization signal having a transition for each address of said address generator; and (b) means for generating a second synchronization signal having a transition, (i) on the first occurrence of each address in said sequence of memory addresses, or (ii) on each occurrence of any or all addresses in said sequence of memory addresses.

Claim 51

The apparatus of claim 43, wherein said digital test signal generator further comprises means responsive to said processor for addressing and storing in said first and second memories digital-test-signal-generating data prior to the generation of said test cycle.

Claim 52

The apparatus of claim 37, wherein said test controller includes: (a) an internal oscillator; (b) a threshold voltage generator responsive to said processor for generating a negative offset voltage to offset the voltages produced by externally generated signals inputted to the testing apparatus; (c) a system clock generator responsive to an external clock signal, said processor, said oscillator and said threshold voltage generator, for generating a system clock, said system clock being derived from said internal oscillator or from the external clock; (d) a command decoder responsive to said processor, for generating system commands to control the functions of said tester; (e) a listen enable generator responsive to said processor and said digital test-signal generators, for controlling the length of said test cycle, and for generating a listen enable signal to enable said functional tester to perform functional tests on said response signal during the generator of said listen enable signal; and (f) a start test cycle generator responsive to said system clock, said listen enable generator, and said command decoder, for starting and stopping said test cycle.

Claim 53

The apparatus of claim 48, wherein said system clock generator includes a divide-by-N counter.

Claim 55

The apparatus of claim 37, wherein said functional tester includes a cyclic redundancy check function tester for generating a digital code representative of the length and character of the serial digital data stream of said response signal, said code representing the signature of said response signal.

Claim 56

An in-circuit testing apparatus adapted for use with a computer for the in-circuit testing of the electrical properties of components in the circuit, the circuit having electrical nodes at which the components are interconnected, the apparatus comprising: (a) means associated with each of selected nodes, and responsive to the computer, for connecting each selected node to one of a plurality of signal lines associated with each selected node, each plurality of signal lines including a response signal line; (b) a digital test-signal generator associated with each said means, for generating a digital test signal for the circuit under test, the output line from each said generator comprising one of the associated signal lines for the node associated with said generator, said means (i) connecting one of said digital test-signal generators to a selected node, and (ii) connecting a selected node to the response signal line; and (c) a test controller responsive to the computer, for generating a test cycle in which digital test signals are applied to selected nodes, the circuit generating a signal on the response signal line in response to the applied test signals.

Claim 57

An in-circuit testing apparatus adapted for use with a computer for the in-circuit testing of the electrical properties of components in the circuit, the circuit having electrical nodes at which the components are interconnected, the apparatus comprising: (a) means associated with each of selected nodes, and responsive to the computer, for connecting each selected node to one of a plurality of signal lines associated with each selected node, each plurality of signal lines including a response signal line; (b) a digital test-signal generator associated with each said means, for generating a digital test signal for the circuit under test, the output line from each said generator comprising one of the associated signal lines for the node associated with said generator, said means (i) connecting one of said digital test-signal generators to a selected node, and (ii) connecting a selected node to the response signal line; and (c) a test controller responsive to the computer, for generating a test cycle in which digital test signals are applied to selected nodes, the circuit generating a signal on the response signal line in response to the applied test signals.

Claim 58

The apparatus according to claim 52 further comprising a functional tester for performing functional tests on said response signal to determine electrical properties of the components of the circuit.

Claim 59

The apparatus of claim 52, wherein said means includes: (a) a test pin contactable with an associated selected electrical node of the circuit; (b) a set of selectable switches connected to each of said test pins, for connecting each test pin to one of its associated signal lines; and (c) switch selecting means responsive to the computer, for selecting said selectable switches.

Claim 60

The apparatus of claim 54, wherein each said set of selectable switches includes a switch for connecting the output from one of said associated digital test-signal generators to its associated test pin.

Claim 61

The apparatus in accordance with claim 53, wherein said functional tester includes: (a) an analog-to-digital converter; (b) a counter for counting (i) the number of cycles in a clock signal that occurred when said response signal is at a logic high state, or (ii) the number of pulses in said response signal that occur in said test cycle; and (c) a cyclic redundancy check generator, for generating a digital code from the serial bit stream of said response signal, said code representing the signature of said signal.

Claim 62

The apparatus of claim 52, wherein said controller includes: (a) a system clock generator responsive to said computer for generating a master system clock for said tester; (b) a command decoder responsive to said computer for generating control signals to control the functions of said tester; (c) a listen enable generator responsive to said computer and said digital test-signal generators, for generating a listen enable signal, to enable said functional tester to perform functional tests on said response signal during the generation of said listen enable signal, and for controlling the length of said test cycle; and (d) a start test cycle generator responsive to said system clock, said command decoder and said listen enable generator, for starting and stoping said test cycle.

Claim 63

The apparatus of claim 54 wherein the set of selectable switches comprises a single switch which selectively connects its associated test pin to the response signal line, the output from each said test-signal generator being removably connected to its associated test pin whereby the associated test pin connected to the response signal line functions alternatively (a) as an input stimulus point to the circuit under test during the entire test cycle, or (b) as an input stimulus point for a first portion of the test cycle, and as an output response signal point for a second portion of the test cycle.

Claim 64

Apparatus adapted for use with a central processor for the in-circuit testing of the electrical properties of components of a circuit under test, said apparatus having a response signal line for monitoring the response signal from the circuit under test, the apparatus comprising: (a) electrical test pins, contactable with electrical nodes in the circuit; (b) a selectable switch associated with each test pin, for selectively connecting the associated said test pin to the response signal line; (c) a plurality of digital test-signal generators, one associated with each of said test pins, for generating at least one digital test signal from a set of test signals, the output line from each said generator adapted for connection to its associated test pin, each said digital test-signal generator including, (i) a memory address generator for generating a sequence of memory addresses during said test cycle, (ii) a first memory responsive to said address generator, for outputting a logic signal to select a digital test signal, said memory having a specified storage location for each digital test signal, said logic signal enabling a transition in said selected test signal, (iii) a second memory responsive to said address generator, for outputting a logic signal to enable and to disable the generation of said selected test signal, (iv) a synchronization signal generator responsive to said memory address generator for generating synchronization signals, and (v) a driver responsive to the output from said first and second memories, and to said synchronization signals, for generating the selected digital test signal and for applying said selected digital test signal to an electrical node of said circuit; (d) switch-selecting means responsive to the central processor, for selecting one said selectable switch to connect a node of said circuit to said response signal line; (e) a test controller responsive to the central processor, for generating a test cycle wherein selected ones of said digital test-signal generators supply test signals to said circuit, thereby to cause the circuit under test to produce a response signal on said response signal line; and (f) a functional tester connected to the response signal line and responsive to the central processor, for testing the signal on the response signal line, to determine electrical properties of the components of the circuit, said functional tester including, (i) an analog-to-digital converter, (ii) a counter for counting (1) the number of cycles in a clock signal that occurred when said response signal is at a logic high state, or (2) the number of pulses in said response signal that occur in said test cycle, and (iii) a cyclic redundancy check generator, for generating a digital code from the serial bit stream of said response signal, said code representing the signature of said response signal.

Claim 65

Apparatus adapted for use with a central processor for the in-circuit testing of the electrical properties of components of a circuit under test, said apparatus having a response signal line for monitoring the response signal from the circuit under test, the apparatus comprising: (a) electrical test pins, contactable with electrical nodes in the circuit; (b) a selectable switch associated with each test pin, for selectively connecting the associated said test pin to the response signal line; (c) a plurality of digital test-signal generators, one associated with each of said test pins, for generating at least one digital test signal from a set of test signals, the output line from each said generator adapted for connection to its associated test pin, each said digital test-signal generator including, (i) a memory address generator for generating a sequence of memory addresses during said test cycle, (ii) a first memory responsive to said address generator, for outputting a logic signal to select a digital test signal, said memory having a specified storage location for each digital test signal, said logic signal enabling a transition in said selected test signal, (iii) a second memory responsive to said address generator, for outputting a logic signal to enable and to disable the generation of said selected test signal, (iv) a synchronization signal generator responsive to said memory address generator for generating synchronization signals, and (v) a driver responsive to the output from said first and second memories, and to said synchronization signals, for generating the selected digital test signal and for applying said selected digital test signal to an electrical node of said circuit; (d) switch-selecting means responsive to the central processor, for selecting one said selectable switch to connect a node of said circuit to said response signal line; (e) a test controller responsive to the central processor, for generating a test cycle wherein selected ones of said digital test-signal generators supply test signals to said circuit, thereby to cause the circuit under test to produce a response signal on said response signal line; and (f) a functional tester connected to the response signal line and responsive to the central processor, for testing the signal on the response signal line, to determine electrical properties of the components of the circuit, said functional tester including, (i) an analog-to-digital converter, (ii) a counter for counting (1) the number of cycles in a clock signal that occurred when said response signal is at a logic high state, or (2) the number of pulses in said response signal that occur in said test cycle, and (iii) a cyclic redundancy check generator, for generating a digital code from the serial bit stream of said response signal, said code representing the signature of said response signal.

Claim 66

The apparatus of claim 59 wherein said selectable switch selectively connects its associated test pin to the response signal line, the output from each said test-signal generator being removably connected to its associated test pin, whereby the associated test pin connected to the response signal line functions alternatively (a) as an input stimulus point to the circuit under test during the entire test cycle, or (b) as an input stimulus point for a first portion of the test cycle, and as an output response point for a second portion of the test cycle.