US3621387A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer-controlled tester for integrated circuit devices
Assignee: Arris Technology Inc
•
Filing: 1969-08-21
•
Granted: 1971-11-16
•
Expires: 1989-08-21
Abstract
Abstract A test apparatus produces a simulated input signal for a device under test and a predicted output signal which that device would correctly product at its output in response to that simulated input. The device output signal and the predicted output signal are compared for logic content, and the amplitude of the device output signal is compared against predetermined reference levels. A separate error signal is produced upon the occurrence of an error in either of these properties in the device output signal. The input and predicted output signals are initially stored into the apparatus from an external computer which also establishes the appropriate clock signals and power supply signals for the device under test. In the embodiment herein shown, the input and output data is preloaded in shift registers and means are provided to sequentially transfer the simulated input and predicted output signals in a time controlled manner from these shift registers to the device and to the output signal comparator.
Inventors
- 👤 Kent F Smith
- 👤 Kay D Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:52
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G01R31/2644; G01R31/2607; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
429 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, in which said predicted output signal producing means comprises second data storage means adapted to have said predicted output signal stored therein in a predetermined pattern defining an output word comprising a plurality of discrete portions, second means operatively connected to said second storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said second data storage means and to sequentially transfer said discrete portions of said predicted output word from said second data storage means to said output signal comparing means and in which said simulated input signal producing means and in which said simulated input signal producing means comprises a third means effective to produce a series of timed control signals, and gating means having an input and an output, said input being operatively connected to said first mentioned data storage means and said third signal and producing means, said gating means bEing effective to produce at said output an output signal upon the operative time coincidence of said third timed signals and an output signal from said first data storage means.
Claim 2
Dependent Claim
429 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, in which said predicted output signal producing means comprises second data storage means adapted to have said predicted output signal stored therein in a predetermined pattern defining an output word comprising a plurality of discrete portions, second means operatively connected to said second storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said second data storage means and to sequentially transfer said discrete portions of said predicted output word from said second data storage means to said output signal comparing means and in which said simulated input signal producing means and in which said simulated input signal producing means comprises a third means effective to produce a series of timed control signals, and gating means having an input and an output, said input being operatively connected to said first mentioned data storage means and said third signal and producing means, said gating means bEing effective to produce at said output an output signal upon the operative time coincidence of said third timed signals and an output signal from said first data storage means.
Claim 3
Dependent Claim
324 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, in which said simulated input signal producing means comprises a third means effective to produce a series of timed control signals, and gating means having an input and an output, said input being operatively connected to said first mentioned data storage means and said third signal producing means, said gating means being effective to produce at said output an output signal upon the operative time coincidence of said third timed signals and an output signal from said first data storage means.
Claim 4
Dependent Claim
324 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, in which said simulated input signal producing means comprises a third means effective to produce a series of timed control signals, and gating means having an input and an output, said input being operatively connected to said first mentioned data storage means and said third signal producing means, said gating means being effective to produce at said output an output signal upon the operative time coincidence of said third timed signals and an output signal from said first data storage means.
Claim 5
Dependent Claim
35 words
The test apparatus of claim 2, further comprising limiting means operatively connected to the output of said gating means and effective to limit the amplitude of the gating means output signal to a predetermined level.
Claim 6
Dependent Claim
80 words
The test apparatus of claim 3, further comprising fourth means effective to produce a series of timed control signals, and second gating means operatively connected to the output of said second data storage means and to said fourth signal producing means and effective upon the operative coincidence of said fourth timed signals and an output signal from said second data storage means to produce a signal at its output, said second gating means output signal defining said predicted output signal.
Claim 7
Dependent Claim
81 words
The test apparatus of claim 4, further comprising means synchronously operatively connected to said first timed control signal producing means and effective to produce a second series of timed control signals, second limiting means operatively connected to said second timed control signal producing means and effective to limit the amplitude of said second timed control signals to a predetermined level, and means operatively connected to said second limiting means and effective to apply said second timed control signals to said device.
Claim 8
Dependent Claim
106 words
The test apparatus of claim 5, in which said timed control signals comprise first and second clock signals having the same predetermined frequency and having a predetermined phase relation with respect to one another, said means for producing said control signals comprising first and second shift registers respectively having data stored therein in a predetermined pattern corresponding to the desired phase relation between said first and second clock signals, and means effective to simultaneously apply input timed signals to said first and sEcond shift registers at the same frequency, thereby to produce said first and second clock signals at said first and second shift registers respectively.
Claim 9
Dependent Claim
83 words
The test apparatus of claim 6, in which said device output signal is to be at one of two discrete logic levels, said comparing means comprising first and second sources of reference signals corresponding to said first and second discrete levels, and means effective to compare the relative amplitudes of said output signal levels and said reference levels and to produce an amplitude error signal in the event that the amplitude of said device output signal differs from either of said reference signals.
Claim 10
Dependent Claim
55 words
The test apparatus of claim 7, in which said comparing means further comprises logic means receiving said predicted output signal and said device output signal, and effective to logically compare these signals and to produce a logic error signal when there is a logical difference between said device output signal and said predicted output signal.
Claim 11
Dependent Claim
37 words
The test apparatus of claim 8, further comprising a source of timed scanning means operative during a predetermined increment during each cycle and effective to sample and test said device output signal only during said cycle increment.
Claim 12
Dependent Claim
28 words
The test apparatus of claim 9, further comprising controllable inhibit means effective when actuated to disable said source of timed scanning signals for a predetermined number of cycles.
Claim 13
Dependent Claim
316 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, further comprising means synchronously operatively connected to said first timed control signal producing means and effective to produce a second series of timed control signals, limiting means operatively connected to said second timed control signal producing means and effective to limit the amplitude of said second timed control means to a predetermined level, and means operatively connected to said limiting means and effective to apply said second timed control signals to said device.
Claim 14
Dependent Claim
316 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, further comprising means synchronously operatively connected to said first timed control signal producing means and effective to produce a second series of timed control signals, limiting means operatively connected to said second timed control signal producing means and effective to limit the amplitude of said second timed control means to a predetermined level, and means operatively connected to said limiting means and effective to apply said second timed control signals to said device.
Claim 15
Dependent Claim
106 words
The test apparatus of claim 11, in which said timed control signals comprise first and second clock signals having the same predetermined frequency and having a predetermined phase relation with respect to one another, said means for producing said control signals comprising first and second shift registers respectively having data stored therein in a predetermined pattern corresponding to the desired phase relation between said first and second clock signals, and means effective to simultaneously apply input timed signals to said first and sEcond shift registers at said predetermined frequency, thereby to produce said first and second clock signals at said first and second shift registers respectively.
Claim 16
Dependent Claim
402 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, in which said device output signal is to be at one of two discrete logic levels, said comparing means comprising first and second sources of reference signals corresponding to said first and second discrete levels, and means effective to compare the relative amplitudes of said device output signal levels and said reference levels and to produce an amplitude error signal in the event that the amplitude of said device output signal differs from either of said reference signals, in which said comparing means further comprises logic means receiving said predicted output signal and said device output signal, and effective to logically compare these signals and to produce a logic error signal when there is a logical difference between said device output signal and said predicted output signal, and further comprising a source of timed scanning signals operative during a predetermined increment during each cycle and effective to sample and test said device output signal only during said cycle increment.
Claim 17
Dependent Claim
402 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, in which said device output signal is to be at one of two discrete logic levels, said comparing means comprising first and second sources of reference signals corresponding to said first and second discrete levels, and means effective to compare the relative amplitudes of said device output signal levels and said reference levels and to produce an amplitude error signal in the event that the amplitude of said device output signal differs from either of said reference signals, in which said comparing means further comprises logic means receiving said predicted output signal and said device output signal, and effective to logically compare these signals and to produce a logic error signal when there is a logical difference between said device output signal and said predicted output signal, and further comprising a source of timed scanning signals operative during a predetermined increment during each cycle and effective to sample and test said device output signal only during said cycle increment.
Claim 18
Dependent Claim
28 words
The test apparatus of claim 13, further comprising controllable inhibit means effective when actuated to disable said source of timed scanning signals for a predetermined number of cycles.
Claim 19
Dependent Claim
274 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a prEdetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, further comprising a source of timed scanning signals operative during a predetermined increment during each cycle and effective to sample and test said device output signal only during said cycle increment.
Claim 20
Dependent Claim
274 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a prEdetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, further comprising a source of timed scanning signals operative during a predetermined increment during each cycle and effective to sample and test said device output signal only during said cycle increment.
Claim 21
Dependent Claim
28 words
The test apparatus of claim 15, further comprising controllable inhibit means effective when actuated to disable said source of timed scanning signals for a predetermined number of cycles.
Claim 22
Dependent Claim
339 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, in which said first data storage means comprises a first shift register having a predetermined pattern stored therein and receiving said timed control signals, said first shift register being effective during a predetermined portion of each cycle as determined by said predetermined pattern to produce a first signal, a second shift register having an internal clock pulse generating circuit and having said input word stored therein, and means for operatively applying said first signal to said internal clock pulse generating circuit in said second shift register, thereby to trigger the latter to produce a shift therein.
Claim 23
Dependent Claim
339 words
A test apparatus for checking the operation of a logic device having an input and output and having the capability of logically processing a signal applied at its input to produce a signal at its output which is a predetermined logic function of the input signal, said apparatus comprising means adapted to be operatively connected to said device input and effective to produce a predetermined simulated input signal, means effective to produce a predicted output signal corresponding to the output signal which the device would correctly produce at its output when said simulated input signal is applied to its input, and means operatively connected to said predicted output signal producing means, adapted to be operatively connected to said device output and effective to compare said predicted output signal with the actual output signal of the device and to produce an error signal in the event that the output signal from the device differs from said predicted output signal, said simulated input signal producing means comprising first data storage means adapted to have said simulated signal stored therein in a predetermined pattern, defining an input word comprising a plurality of discrete portions, means operatively connected to said data storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said storage means and to sequentially transfer said discrete portions of said input word from said storage means to the input of said device, in which said first data storage means comprises a first shift register having a predetermined pattern stored therein and receiving said timed control signals, said first shift register being effective during a predetermined portion of each cycle as determined by said predetermined pattern to produce a first signal, a second shift register having an internal clock pulse generating circuit and having said input word stored therein, and means for operatively applying said first signal to said internal clock pulse generating circuit in said second shift register, thereby to trigger the latter to produce a shift therein.
Claim 24
Dependent Claim
99 words
The apparatus of claim 17 in which said predicted output signal producing means comprises second data storage means adapted to have said predicted output signal stored therein in a predetermined pattern defining an output word comprising a plurality of discrete portions, second means operatively connected to said second storage means and effective to produce a series of timed control signals, and means effective to operatively apply said control signals to said second data storage means and to sequentially transfer said discrete portions of said predicted output word from said second data storage means to said output signal comparing means.
Claim 25
Dependent Claim
87 words
The test apparatus of claim 17, in which said simulated input signal producing means comprises a third means effective to produce a series of timed control signals, and gating means having an input and an output, said input being operatively connected to said first mentioned data storage means and said third signal producing means, said gating means being effective to produce at said output an output signal upon the operative time coincidence of said third timed signals and an output signal from said first data storage means.
References Cited (Backward Citations)
US3219927A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-15 | 1975-05-17 | 1975-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-15 | 1979-05-17 | 1979-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-15 | 1983-05-17 | 1983-11-16 | $7700.00 | Window Closed / Lapsed |