US3763430A
Expired / Lapsed
US
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Circuit testing method and apparatus
Assignee: Unisys Corp
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Filing: 1972-01-14
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Granted: 1973-10-02
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Expires: 1992-01-14
Abstract
Abstract Method and apparatus for testing complexes of circuits, such as printed circuit boards and the like, for continuity of desired circuits and absence of short circuiting are provided. A circuit board having a plurality of possible circuit nodes has each node scanned sequentially by a step switch or the like. As each node is scanned in one embodiment, all lower order nodes are electrically interconnected, and means are provided for sensing closed circuit and open circuit signals between the scanned node and interconnected nodes. Logic is provided for ''''rejecting'''' a board if both the closed circuit sensing and open circuit sensing are either within or without acceptable limits and for ''''accepting'''' a board if either is within the limits when the other is without. Signals representative of the presence or absence of a circuit for each node as scanned is applied to a cyclic shift register having fewer bits than the number of circuit nodes. After all the nodes have been scanned, the final word in the cyclic shift register is compared with an input word for providing an output signal indicative of identity or lack of identity of the measured word and the comparison word. By sensing continuity between each circuit node sequentially while all lower order nodes are interconnected the lowest order node in each continuous circuit is identified, and an acceptable circuit can be distinguished from an unacceptable circuit without exploring each circuit path separately, thereby greatly reducing the circuit testing time.
Inventors
- 👤 C Terrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2801; G01R31/2805; G01R31/50
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
114 words
In a circuit testing apparatus for testing a circuit arrangement having a plurality of circuit nodes comprising means for applying a test signal to a circuit node, means for electrically interconnecting all circuit nodes of lower order than the circuit node to which the signal is applied at each instant, means for sensing the presence or absence of the test signal on the interconnected nodes, and means for storing indicia of said presence or absence, an improved scanning cycle means comprising: means for applying the test signal successively without interruption to each circuit node of the plurality of circuit nodes regardleSs of the presence or absence of the test signal on the interconnected nodes.
Claim 2
Dependent Claim
114 words
In a circuit testing apparatus for testing a circuit arrangement having a plurality of circuit nodes comprising means for applying a test signal to a circuit node, means for electrically interconnecting all circuit nodes of lower order than the circuit node to which the signal is applied at each instant, means for sensing the presence or absence of the test signal on the interconnected nodes, and means for storing indicia of said presence or absence, an improved scanning cycle means comprising: means for applying the test signal successively without interruption to each circuit node of the plurality of circuit nodes regardleSs of the presence or absence of the test signal on the interconnected nodes.
Claim 3
Dependent Claim
166 words
Circuit testing apparatus for testing a circuit arrangement having a plurality of circuit nodes comprising: means for applying a forcing voltage to each circuit node successively without interruption; means for electrically interconnecting all circuit nodes of lower order than the circuit node to which the voltage is applied at each instant; voltage sensing means for sensing the presence or absence of a conductive path between the test circuit node and the interconnected circuit nodes having a greater conductivity than a preselected value; current sensing means for sensing the presence or absence of a current path between the test circuit node and the interconnected circuit nodes having a conductivity greater than a preselected value; and means for generating a rejection signal if both the voltage sensing means and current sensing means indicate a conductive path inside or outside of acceptable limits and for generating an acceptance signal if only one of either the voltage sensing means or current sensing means indicates a conductive path within acceptable limits.
Claim 4
Dependent Claim
166 words
Circuit testing apparatus for testing a circuit arrangement having a plurality of circuit nodes comprising: means for applying a forcing voltage to each circuit node successively without interruption; means for electrically interconnecting all circuit nodes of lower order than the circuit node to which the voltage is applied at each instant; voltage sensing means for sensing the presence or absence of a conductive path between the test circuit node and the interconnected circuit nodes having a greater conductivity than a preselected value; current sensing means for sensing the presence or absence of a current path between the test circuit node and the interconnected circuit nodes having a conductivity greater than a preselected value; and means for generating a rejection signal if both the voltage sensing means and current sensing means indicate a conductive path inside or outside of acceptable limits and for generating an acceptance signal if only one of either the voltage sensing means or current sensing means indicates a conductive path within acceptable limits.
Claim 5
Dependent Claim
141 words
A circuit testing apparatus as defined in claim 2 further comprising: means for producing a first logical signal representative of a conductive path between the test circuit node and the interconnected circuit nodes and a second logical signal representative of absence of a conductive path therebetween; a cyclic shift register connected to the means for producing logical signals for generating a number at the end of a testing sequence wherein all circuit nodes are successively tested, the number having fewer bits than the number of circuit nodes tested; means for inserting into the apparatus a number representative of a circuit having selected interconnections; and means for comparing the inserted number with the number recorded in the shift register at the end of a testing sequence and for producing a comparison signal indicative of identity or lack of identity of the numbers.
Claim 6
Dependent Claim
83 words
A circuit testing apparatus as defined in claim 3 further comprising: means for generating a rejection signal if both the voltage sensing means and current sensing means indicate a conductive path inside or outside of acceptable limits, and for generating an acceptance signal if only one of either the voltage sensing means or current sensing means indicates a conductive path within acceptable limits; and means for combining the rejection signal and acceptance signal with the comparison signal for accepting or rejecting a circuit.
Claim 7
Dependent Claim
44 words
A circuit testing apparatus as defined in Claim 4 wherein the means for applying a test signal to each circuit node successively comprises a step switch; and wherein the means for electrically interconnecting all circuit nodes of lower order comprises a step latch switch.
Claim 8
Dependent Claim
122 words
Circuit testing apparatus for testing a circuit arrangement having a plurality of circuit nodes comprising: means for applying a test signal to each circuit node successively without interruption; means for electrically interconnecting all circuit nodes of lower order than the circuit node to which the signal is applied at each instant; means for generating a first logical signal representative of a closed circuit between the circuit node being tested and the interconnected lower order circuit nodes and a second logical signal representative of an open circuit therebetween; and means for comparing a logical word formed of a sequence of first and second logical signals produced by the means for generating with a second logical word representative of a circuit having selected interconnections.
Claim 9
Dependent Claim
122 words
Circuit testing apparatus for testing a circuit arrangement having a plurality of circuit nodes comprising: means for applying a test signal to each circuit node successively without interruption; means for electrically interconnecting all circuit nodes of lower order than the circuit node to which the signal is applied at each instant; means for generating a first logical signal representative of a closed circuit between the circuit node being tested and the interconnected lower order circuit nodes and a second logical signal representative of an open circuit therebetween; and means for comparing a logical word formed of a sequence of first and second logical signals produced by the means for generating with a second logical word representative of a circuit having selected interconnections.
Claim 10
Dependent Claim
31 words
A circuit testing apparatus as defined in claim 6 further comprising: means for reducing the sequence of signals to a number having fewer bits than the number of circuit nodes tested.
Claim 11
Dependent Claim
123 words
Circuit testing apparatus for testing a circuit having a plurality of nodEs comprising: means for selectively interconnecting circuit nodes for dividing a plurality of circuit nodes into a first set of externally connected nodes and a second set of externally non-connected nodes; means for generating a test signal; means for applying the test signal to each circuit node in the second set successively without interruption over substantially the entire plurality of circuit nodes and in coordination therewith increasing by one the number of nodes in one set and decreasing by one the nodes in the other set; means for sensing the presence of absence of the signal on the first set of externally connected nodes; and means for generating a signal indicative thereof.
Claim 12
Dependent Claim
123 words
Circuit testing apparatus for testing a circuit having a plurality of nodEs comprising: means for selectively interconnecting circuit nodes for dividing a plurality of circuit nodes into a first set of externally connected nodes and a second set of externally non-connected nodes; means for generating a test signal; means for applying the test signal to each circuit node in the second set successively without interruption over substantially the entire plurality of circuit nodes and in coordination therewith increasing by one the number of nodes in one set and decreasing by one the nodes in the other set; means for sensing the presence of absence of the signal on the first set of externally connected nodes; and means for generating a signal indicative thereof.
Claim 13
Dependent Claim
40 words
Circuit testing apparatus as defined in claim 8 wherein the means for successively scanning comprises means for transferring the node just tested from the second set to the first set until all nodes except a final test node are interconnected.
Claim 14
Dependent Claim
71 words
Circuit testing apparatus as defined in claim 9 wherein the means for sensing a signal comprises: a voltage sensor for sensing the presence or absence of a voltage of selected magnitude between the test node and the first set of externally connected nodes; and a current sensor for sensing the presence or absence of a current of selected magnitude between the test node and the first set of externally connected nodes.
Claim 15
Dependent Claim
48 words
Circuit testing apparatus as defined in claim 8 further comprising: means for temporarily recording a history of the signals sensed on the first set as a number; means for generating a number representative of an acceptable circuit; and means for comparing the recorded number with the generated number.
Claim 16
Dependent Claim
26 words
A circuit testing apparatus as defined in claim 11 wherein the means for temporarily recording comprises a cyclic shift register connected to the means for sensing.
Claim 17
Independent Claim
110 words
A method of testing a circuit having a plurality of circuit nodes comprising the steps of: applying a signal to a first circuit node; interconnecting a plurality of other circuit nodes; sensing the presence or absence of the signal on the interconnected nodes; interconnecting the first circuit node with the previously interconnected circuit nodes; applying a signal to a second circuit node; sensing the presence or absence of the signal on the new set of interconnected nodes; and sequentially repeating the interconnecting of circuit nodes and applying of signals over the entire plurality of circuit nodes without interruption regardless of presence or absence of the signal on the interconnected nodes.
Claim 18
Independent Claim
110 words
A method of testing a circuit having a plurality of circuit nodes comprising the steps of: applying a signal to a first circuit node; interconnecting a plurality of other circuit nodes; sensing the presence or absence of the signal on the interconnected nodes; interconnecting the first circuit node with the previously interconnected circuit nodes; applying a signal to a second circuit node; sensing the presence or absence of the signal on the new set of interconnected nodes; and sequentially repeating the interconnecting of circuit nodes and applying of signals over the entire plurality of circuit nodes without interruption regardless of presence or absence of the signal on the interconnected nodes.
Claim 19
Dependent Claim
39 words
A method of testing a circuit as defined in claim 13 further comprising: recording a historical sequence of signals sensed on the interconnected nodes; and comparing the recorded signals with a plurality of signals representative of an acceptable circuit.
Claim 20
Dependent Claim
35 words
A method of testing a circuit as defined in claim 14 wherein the recording step further comprises reducing the sequence of signals to a number having fewer bits than the number of circuit nodes tested.
Claim 21
Dependent Claim
52 words
A method of testing as defined in claim 13 comprising the step of: repeating the interconnecting of circuit nodes, applying of signals, and sensing the presence or absence of the signal over substantially the entire plurality of circuit nodes in a scan sequence different from the first sequence of interconnecting and applying.
Claim 22
Independent Claim
85 words
A method of testing a circuit having a plurality of circuit nodes comprising the steps of: sequentially sensing the presence or absence of electrical continuity between each successive circuit node and all circuit nodes of lower order than the first circuit node for distinguishing all lowest order circuit nodes in each continuous circuit from all other circuit nodes; and comparing the location of lowest order circuit nodes so distinguished with desired locations of lowest order circuit nodes without searching for members of each circuit string.
Claim 23
Independent Claim
85 words
A method of testing a circuit having a plurality of circuit nodes comprising the steps of: sequentially sensing the presence or absence of electrical continuity between each successive circuit node and all circuit nodes of lower order than the first circuit node for distinguishing all lowest order circuit nodes in each continuous circuit from all other circuit nodes; and comparing the location of lowest order circuit nodes so distinguished with desired locations of lowest order circuit nodes without searching for members of each circuit string.
Claim 24
Dependent Claim
100 words
Circuit testing apparatus for a circuit board having a plurality of circuit nodes comprising: means for distinguishing all lowest order circuit nodes in each continuous circuit from all other circuit nodes; and means for comparing the locations of lowest order circuit nodes so distinguished with desired locations of lowest order circuit nodes without searching for members of each circuit string; and wherein the means for identifying all lowest order nodes comprises means for sequentially sensing the presence or absence of electrical continuity between each successive circuit node and all circuit nodes of lower order than each successive circuit node respectively.
Claim 25
Dependent Claim
100 words
Circuit testing apparatus for a circuit board having a plurality of circuit nodes comprising: means for distinguishing all lowest order circuit nodes in each continuous circuit from all other circuit nodes; and means for comparing the locations of lowest order circuit nodes so distinguished with desired locations of lowest order circuit nodes without searching for members of each circuit string; and wherein the means for identifying all lowest order nodes comprises means for sequentially sensing the presence or absence of electrical continuity between each successive circuit node and all circuit nodes of lower order than each successive circuit node respectively.
Claim 26
Dependent Claim
78 words
A circuit testing apparatus for testing a circuit arrangement having a plurality of circuit nodes comprising: scanning cycle means for applying a test signal successively without interruption to each circuit node of the plurality of circuit nodes; means for electrically interconnecting all circuit nodes of lower order than the circuit node to which the signal is applied at each instant; and sensor means for sensing the presence or absence of the test signal on the lower order nodes.
Claim 27
Dependent Claim
78 words
A circuit testing apparatus for testing a circuit arrangement having a plurality of circuit nodes comprising: scanning cycle means for applying a test signal successively without interruption to each circuit node of the plurality of circuit nodes; means for electrically interconnecting all circuit nodes of lower order than the circuit node to which the signal is applied at each instant; and sensor means for sensing the presence or absence of the test signal on the lower order nodes.
Claim 28
Independent Claim
93 words
A method of testing the acceptability of a circuit arrangement having a plurality of circuit nodes comprising the steps of: selecting an arbitrary ordered sequence for all of the circuit nodes; applying a test signal to one of the circuit nodes; electrically interconnecting all circuit nodes of lower order than the circuit node to which the signal is applied at each instant; sensing the presence or absence of the test signal on the interconnected nodes; and applying the test signal successively without interruption to each circuit node in the sequence of circuit nodes.
Claim 29
Independent Claim
93 words
A method of testing the acceptability of a circuit arrangement having a plurality of circuit nodes comprising the steps of: selecting an arbitrary ordered sequence for all of the circuit nodes; applying a test signal to one of the circuit nodes; electrically interconnecting all circuit nodes of lower order than the circuit node to which the signal is applied at each instant; sensing the presence or absence of the test signal on the interconnected nodes; and applying the test signal successively without interruption to each circuit node in the sequence of circuit nodes.
Claim 30
Dependent Claim
53 words
A method as defined in claim 20 comprising the additional steps of: selecting a second arbitrary ordered sequence for all of the circuit nodes different from the first ordered sequence; and repeating the steps of applying, interconnecting, and sensing successively with respect to each circuit node in the second sequence of circuit nodes.
Claim 31
Dependent Claim
18 words
A method as defined in claim 21 wherein the second sequence is the reverse of the first sequence.
Claim 32
Dependent Claim
92 words
In a method for testing a circuit arrangement having a plurality of circuit nodes including the steps of sensing the presence or absence of a test signal between one circuit node and interconnected circuit nodes of lower order than the one circuit node, and generating a comparison signal indicative of the presence or absence, the improvement comprising: successively sensing the presence or absence of the test signal between each circuit node and its corresponding interconnected lower order nodes over at least two sequences of circuit nodes that are different from each other.
Claim 33
Dependent Claim
92 words
In a method for testing a circuit arrangement having a plurality of circuit nodes including the steps of sensing the presence or absence of a test signal between one circuit node and interconnected circuit nodes of lower order than the one circuit node, and generating a comparison signal indicative of the presence or absence, the improvement comprising: successively sensing the presence or absence of the test signal between each circuit node and its corresponding interconnected lower order nodes over at least two sequences of circuit nodes that are different from each other.
Claim 34
Dependent Claim
25 words
In a method for testing as defined in claim 23 the further improvement wherein one of the sequences is the reverse of the other sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-01 | 1977-04-02 | 1977-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-01 | 1981-04-02 | 1981-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-01 | 1985-04-02 | 1985-10-02 | $7700.00 | Window Closed / Lapsed |