Bit line decoder architecture for NOR-type memory array

Claim 2

A bit line decoder for sensing states of memory cells of a memory array, the bit line decoder comprising: R first sub-decoders that communicate with R memory sub-arrays of said memory array, respectively, where R is an integer greater than 1, wherein each of said R first sub-decoders includes D control devices that communicate with S bit lines of said memory array, where D and S integers greater than 2, and S>D, (S-1) of said D control devices are connected in series with each other forming (S-2) junctions, and said (S-2) junctions are directly connected to (S-2) of said S bit lines; R isolation circuits each having (i) first ends that communicate with said R first sub-decoders, respectively, and (ii) second ends, wherein said second ends of a first of said R isolation circuits communicate with corresponding said second ends of (R-1) or said R isolation circuits; a second sub-decoder that communicates with one of said R first sub-decoders via said second ends of said R isolation circuits; and a sensing circuit that (i) communicates with said second sub-decoder and (ii) senses a state of one of said memory cells located within one of said R memory sub-arrays via said second ends.

Claim 3

The bit line decoder of claim 1 further comprising a control module that generates first control signals, wherein the first control signals select one of said R isolation circuits that communicates with said one of said R first sub-decoders.

Claim 4

The bit line decoder of claim 2 wherein each of said R first sub-decoders includes first control devices arranged in P of L levels of said bit line decoder, and wherein said second sub-decoder includes second control devices arranged in Q of said L levels, where P and Q are integers greater than or equal to 1, and (P+Q)=L.

Claim 5

The bit line decoder of claim 3 wherein said first control devices are greater in number than said second control devices.

Claim 6

An integrated circuit (IC) comprising: the bit line decoder of claim 3 ; and said memory array, wherin said memory array communicates with B bit lines, and wherein said R memory sub-arrays communicate with said R first sub-decoders via R sets of S of said B bit lines, respectively, where S is an integer greater than 1, and B=R*S.

Claim 7

The IC of claim 5 wherein when a sum of (i) said first and (ii) second control devices is D, and a K th of said L levels includes 2 K of said D control devices, S=(2 L +1), where D is an integer greater than 2, and 1≦K≦L.

Claim 8

The IC of claim 6 wherein said control module generates second control signals that (i) deselect half of said D control devices and (ii) select two bit lines from one of said R sets, and wherein said two bit lines communicate with said one of said memory cells located within said one of said R memory sub-arrays that communicates with said one of said R first sub-decoders via said one of said R sets.

Claim 9

The IC of claim 7 wherein said sensing circuit applies a potential difference across said two bit lines, senses current that flows through said one of said memory cells, and determines a state of said one of said memory cells based on said current.

Claim 10

The IC of claim 7 wherein said sensing circuit applies (i) a first potential to M bit lines from said one of said R sets that are on a first side of said one of said memory cells and (ii) a second potential to N bit lines from said one of said R sets that are on a second side of said one of said memory cells, where M and N are integers greater than or equal to 1, and (M+N)=S.

Claim 11

The IC of claim 9 wherein said sensing circuit (i) measures current that flows through said one of said memory cells and (ii) determines said state of said one of said memory cells based on said current.

Claim 12

The IC of claim 5 wherein: when L=2, a number of said second control devices is 2, and a number of said first control devices is D, where S=(D+1), and log 2 D is an integer greater than 2.

Claim 13

The IC of claim 11 wherein: said control module generates second control signals that (i) deselect one of said second control devices, (ii) deselect two of said first control devices, and (iii) select two bit lines from one of said R sets, and said two bit lines communicate with said one of said memory cells located within said one of said R memory sub-arrays that communicates with said one of said R first sub-decoders via said one of said R sets.

Claim 14

The IC of claim 12 wherein said sensing circuit applies a potential difference across said two bit lines, senses current that flows through said one of said memory cells, and determines a state of said one of said memory cells based on said current.

Claim 15

The IC of claim 12 wherein said sensing circuit applies (i) a first potential to M bit lines from said one of said R sets that are on a first side of said one of said memory cells and (ii) a second potential to N bit lines from said one of said R sets that are on a second side of said one of said memory cells, where M and N are integers greater than or equal to 1, and (M+N)=S.

Claim 16

The IC of claim 14 wherein said sensing circuit (i) measures current that flows through said one of said memory cells and (ii) determines said state of said one of said memory cells based on said current.

Claim 19

The method of claim 16 further comprising: generating first control signals; selecting one of said R isolation circuits based on said first control signals; and communicating with said one of said R first sub-decoders based on said first control signals.

Claim 20

The method of claim 17 comprising: providing first control devices; arranging said first control devices in each of said R first sub-decoders in P of L levels of a bit line decoder, where P and L are integers greater than or equal to 1; providing second control devices; and arranging said second control devices in said second sub-decoder in Q of said L levels, where (P+Q)=L.

Claim 21

The method of claim 18 further comprising providing said first control devices that are greater in number than said second control devices.

Claim 22

The method of claim 18 further comprising: communicating with said memory array via B bit lines, where B is an integer greater than 1; and communicating with said R memory sub-arrays and said R first sub-decoders via R sets of S of said B bit lines, respectively, where S is an integer greater than 1, and B=R*S.

Claim 23

The method of claim 20 further comprising providing 2 K of said D control devices in a K th of said L levels when a sum of said first and second control devices is D and S=(2 L +1), where D is an integer greater than 2, and 1≦K≦L.

Claim 24

The method of claim 21 further comprising: generating second control signals; deselecting half of said D control devices based on said second control signals; selecting two bit lines from one of said R sets based on said second control signals; and communicating with said one of said memory cells via said two bit lines, wherein said one of said memory cells is located within said one of said R memory sub-arrays that communicates with said one of said R first sub-decoders via said one of said R sets.

Claim 25

The method of claim 22 further comprising: applying a potential difference across said two bit lines using said sensing circuit; sensing current that flows through said one of said memory cells using said sensing circuit; and determing a state of said one of said memory cells based on said current using said sensing circuit.

Claim 26

The method of claim 22 further comprising using said sensing circuit to: apply a first potential to M bit lines from said one of said R sets that are on a first said of said one of said memory cells; and apply a second potential to N bit lines from said one of said R sets that are on a second side of said one of said memory cells, where M and N are integers greater than or equal to 1, and (M+N)=S.

Claim 27

The method of claim 24 further comprising using said sensing circuit to: measure current that flows through said one of said memory cells; and determine said state of said one of said memory cells based on said current.

Claim 28

The method of claim 20 wherein: when L=2, a number of said second control devices is 2, and a number of said first control devices is D, where S=(D+ 1 ), and log 2 D is an integer greater than 2.

Claim 29

The method of claim 26 further comprising: generating second control signals; deselecting one of said second control devices based on said second control signals; deselecting two of said first control devices based on said second control signals; selecting two bit lines from one of said R sets based on said second control signals; and communicating with said one of said memory cells via said two bit lines, wherein said one of said memory cells is located within said one of said R memory sub-arrays that communicates with said one of said R first sub-decoders via said one of said R sets.

Claim 30

The method of claim 27 further comprising using said sensing circuit to: apply a potential difference across said two bit lines; sense current that flows through said one of said memory cells; and determine a state of said one of said memory cells based on said current.

Claim 31

The method of claim 27 further comprising using said sensing circuit to: apply a first potential to M bits lines from said one of said R sets that are on a second side of said one of said memory cells, where M and N are integers greater than or equal to 1, and (M+N)=S.

Claim 32

The method of claim 29 further comprising using said sensing circuit to: measure current that flows through said one of said memory cells; and determine said state of said one of said memory cells based on said current.

Claim 33

A bit line decoder for sensing states of memory cells of a memory array, the bit line decoder comprising: R first sub-decoder means for sensing said states, wherein said R first sub-decoder means communicate with R memory sub-arrays of said memory array, respectively, where R is an integer greater than 1, wherein each of said R first sub-decoder means includes D control means that communicate with S bit lines of said memory array, where D and S are integers greater than 2, and S>D, (S-1) of said D control means are connected in series with each other forming (S-2) junctions, and said (S-2) junctions are directly connected to (S-2) of said S bit lines; R isolating means for isolating said R first sub-decoder means, wherein each of said R isolating means have (i) first ends that communicate with said R first sub-decoder means, respectively, and (ii) second ends, wherein said second ends of a first of said R isolating means communicate with corresponding said second ends of (R-1) of said R isolating means; second sub-decoder means for sensing said states, wherein said second sub-decoder means communicates with one of said R first sub-decoder means via said second ends of said R isolation means; and sensing means in communication with said second sub-decoder means, said sensing means for sensing a state of one of said memory cells located within one of said R memory sub-arrays via said second ends.

Claim 34

A bit line decoder for sensing states of memory cells of a memory array, the bit line decoder comprising: R first sub-decoder means for sensing said states, wherein said R first sub-decoder means communicate with R memory sub-arrays of said memory array, respectively, where R is an integer greater than 1, wherein each of said R first sub-decoder means includes D control means that communicate with S bit lines of said memory array, where D and S are integers greater than 2, and S>D, (S-1) of said D control means are connected in series with each other forming (S-2) junctions, and said (S-2) junctions are directly connected to (S-2) of said S bit lines; R isolating means for isolating said R first sub-decoder means, wherein each of said R isolating means have (i) first ends that communicate with said R first sub-decoder means, respectively, and (ii) second ends, wherein said second ends of a first of said R isolating means communicate with corresponding said second ends of (R-1) of said R isolating means; second sub-decoder means for sensing said states, wherein said second sub-decoder means communicates with one of said R first sub-decoder means via said second ends of said R isolation means; and sensing means in communication with said second sub-decoder means, said sensing means for sensing a state of one of said memory cells located within one of said R memory sub-arrays via said second ends.

Claim 35

The bit line decoder of claim 31 further comprising selecting means for generating first control signals, wherein said first control signals select one of said R isolating means that communicates with said one of said R first sub-decoder means.

Claim 36

The bit line decoder of claim 32 wherein each of said R first sub-decoder means includes first control means for selecting B bit lines arranged in P of L levels of said bit line decoder, and wherein said second sub-decoder means includes second control means for selecting said B bit lines arranged in Q of said L levels, where B is an integer greater than 1, P and Q are integers greater than or equl to 1, and (P+Q)=L.

Claim 37

The bit line decoder of claim 33 wherein said first control means are greater in number than said second control means.

Claim 38

An integrated circuit (IC) comprising: the bit line decoder of claim 33 ; and said memory array, wherein said memory array communicates with said B bit lines, and wherein said R memory sub-arrays communicate with said R first sub-decoder means via R sets of S of said B bit lines, respectively, where S is an integer greater than 1, and B=R*S.

Claim 39

The IC of claim 35 wherein when a sum of said first and second control means is D and a K th of said L levels includes 2 K of said D control means, S=(S I +1), where D is an integer greater than 2, and 1≦K ≦L.

Claim 40

The IC of claim 36 wherein said selecting means generates second control signals that (i) deselect half of said D control means and (ii) select two bit lines from one of said R sets, and wherein said two bit lines communicate with said one of said memory cells located within said one of said R memory sub-arrays that communicates with said one of said R first sub-decoder means via said one of said R sets.

Claim 41

The IC of claim 37 wherein said sensing means applies a potential difference across said two bit lines, senses current that flows through said one of said memory cells, and determines a state of said one of said memory cells based on said current.

Claim 42

The IC of claim 37 wherein said sensing means applies (i) a first potential to M bit lines from said one of said R sets that are on a first side of said one of said memory cells and (ii) a second potential to N bit lines from said one of said R sets that are on a second side of said one of said memory cells, where M and N are integers greater than or equal to 1, and (M+N)=S.

Claim 43

The IC of claim 39 wherein said sensing means (i) measures current that flows through said one of said memory cells and (ii) determines said state of said one of said memory cells based on said current.

Claim 44

The IC of claim 35 wherein: when L=2, a number of said second control means is 2, and a number of said first control means is D, where S=(D+), and log 2 D is an integer greater than 2.

Claim 45

The IC of claim 41 wherein: said selecting means generates second control signals that (i) deselect one of said second control means, (ii) deselect two of said first control means, and (iii) select two bit lines from one of said R sets, and said two bit lines communicate with said one of said memory cells located within said one of said R memory sub-arrays that communicates with said one of said R first sub-decoder means via said one of said R sets.

Claim 46

The IC of claim 42 wherein said sensing means (i) applies a potential difference across said two bit lines, senses current that flows through said one of said memory cells, and (ii) determines a state of said one of said memory cells based on said current.

Claim 47

The IC of claim 42 wherein said sensing means applies (i) a first potential to M bit lines from said one of said R sets that are on a first side of said one of said memory cells and (ii) a second potential to N bit lines from said one of said R sets that are on a second side of said one of said memory cells, where M and N are integers greater than or equal to 1, and (M+N)=S.

Claim 48

The IC of claim 44 wherein said sensing means (i) measures current that flows through said one of said memory cells and (ii) determines said state of said one of said memory cells based on said current.