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Decoding structure for a memory device with a control code
Assignee: Micron Technology Inc
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Filing: 2002-12-27
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Granted: 2005-10-25
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Expires: 2022-12-27
Abstract
Abstract A decoding structure for a memory device with a control code is used in a memory including a matrix of memory cells grouped into pages to each of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel. The decoding structure selectively connects each reading element to a plurality of memory cells, and selectively connects each memory cell to a plurality of reading elements.
Inventors
- 👤 Emanuele Confalonieri
- 👤 Marco Sforzin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:27
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1072
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
82 words
A decoding structure for a memory device with a control code and including a matrix of memory cells grouped into pages to each one of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel, the decoding structure comprising: a first circuit for selectively connecting each reading element to a plurality of memory cells; and a second circuit for selectively connecting each memory cell to the plurality of reading elements.
Claim 2
Dependent Claim
82 words
A decoding structure for a memory device with a control code and including a matrix of memory cells grouped into pages to each one of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel, the decoding structure comprising: a first circuit for selectively connecting each reading element to a plurality of memory cells; and a second circuit for selectively connecting each memory cell to the plurality of reading elements.
Claim 3
Dependent Claim
79 words
The decoding structure according to claim 1 wherein the first and second circuits include a plurality of selection elements grouped into blocks each organized into a tree with a plurality of levels, the tree having a root connected to a corresponding reading element and a last level connected to corresponding memory cells, and wherein at least one level starting from the last level is shared in a set formed by a plurality of trees associated with different reading elements.
Claim 4
Dependent Claim
37 words
The decoding structure according to claim 2 wherein each tree further includes an intermediate level directly connected to the at least one shared level, the intermediate level being partially shared among the trees of a corresponding set.
Claim 5
Dependent Claim
79 words
The decoding structure according to claim 3 wherein each level includes a set of branches for each branch of an immediately higher level, wherein the intermediate level has each set of branches with an exception of a first set of branches that is shared among the trees of the corresponding set of branches, and wherein the branches of the first set are connected in a staggered way to corresponding sets of branches of the at least one shared level.
Claim 6
Dependent Claim
60 words
The decoding structure according to claim 4 wherein said first and second circuits comprise a first decoder circuit for generating a plurality of first selection signals each one for simultaneously controlling a corresponding selection element in each tree, and wherein corresponding selection elements in each non-shared level of the trees of each set are controlled by different first selection signals.
Claim 7
Dependent Claim
52 words
The decoding structure according to claim 5 wherein the first selection signals associated with each non-shared level are ordered according to a circular list, and wherein the corresponding selection elements in each non-shared level of the trees of each set are controlled by adjacent first selection signals according to the circular list.
Claim 8
Dependent Claim
97 words
The decoding structure according to claim 6 wherein each page includes a plurality of words, wherein said first and second circuits comprise a second decoder circuit for generating a plurality of second selection signals each one for controlling outputting of a correspondent word of read pages, and wherein the first decoder circuit is controlled by a first portion of a word address formed by a plurality of bits and the second decoder circuit is controlled by a value obtained by adding at least one bit having a preset value to a second portion of the word address.
Claim 9
Dependent Claim
65 words
A memory device comprising: a matrix of memory cells grouped into pages to each of which a block of control information is associated; a plurality of reading elements for reading a plurality of pages in parallel; and a decoding structure for selectively connecting each reading element to a plurality of memory cells, and for selectively connecting each memory cell to the plurality of reading elements.
Claim 10
Dependent Claim
65 words
A memory device comprising: a matrix of memory cells grouped into pages to each of which a block of control information is associated; a plurality of reading elements for reading a plurality of pages in parallel; and a decoding structure for selectively connecting each reading element to a plurality of memory cells, and for selectively connecting each memory cell to the plurality of reading elements.
Claim 11
Dependent Claim
77 words
The memory device according to claim 8 wherein said decoding structure comprises a plurality of selection elements grouped into blocks each organized into a tree with a plurality of levels, the tree having a root connected to a corresponding reading element and a last level connected to corresponding memory cells, and wherein at least one level starting from the last level is shared in a set formed by a plurality of trees associated with different reading elements.
Claim 12
Dependent Claim
37 words
The memory device according to claim 9 wherein each tree further includes an intermediate level directly connected to the at least one shared level, the intermediate level being partially shared among the trees of a corresponding set.
Claim 13
Dependent Claim
79 words
The memory device according to claim 10 wherein each level includes a set of branches for each branch of an immediately higher level, wherein the intermediate level has each set of branches with an exception of a first set of branches that is shared among the trees of the corresponding set of branches, and wherein the branches of the first set are connected in a staggered way to corresponding sets of branches of the at least one shared level.
Claim 14
Dependent Claim
58 words
The memory device according to claim 11 wherein said decoder structure comprises a first decoder circuit for generating a plurality of first selection signals each one for simultaneously controlling a corresponding selection element in each tree, and wherein corresponding selection elements in each non-shared level of the trees of each set are controlled by different first selection signals.
Claim 15
Dependent Claim
52 words
The memory device according to claim 12 wherein the first selection signals associated with each non-shared level are ordered according to a circular list, and wherein the corresponding selection elements in each non-shared level of the trees of each set are controlled by adjacent first selection signals according to the circular list.
Claim 16
Dependent Claim
96 words
The memory device according to claim 13 wherein each page includes a plurality of words, wherein said decoder structure further comprises a second decoder circuit for generating a plurality of second selection signals each one for controlling outputting of a correspondent word of read pages, and wherein the first decoder circuit is controlled by a first portion of a word address formed by a plurality of bits and the second decoder circuit is controlled by a value obtained by adding at least one bit having a preset value to a second portion of the word address.
Claim 17
Dependent Claim
41 words
The memory device according to claim 8 further comprising an output circuit connected to said decoder structure for outputting a plurality of words of the read pages in a burst mode starting from a first word identified by a word address.
Claim 18
Dependent Claim
19 words
The memory device according to claim 8 wherein each of said memory cells comprises a non-volatile multilevel memory cell.
Claim 19
Dependent Claim
98 words
A memory device comprising: a matrix of non-volatile multilevel memory cells grouped into pages to each of which a block of control information is associated; a plurality of reading elements for reading a plurality of pages in parallel; a decoding structure for selectively connecting each reading element to a plurality of memory cells, and for selectively connecting each memory cell to the plurality of reading elements; and an output circuit connected to said decoder structure for outputting a plurality of words of read pages in a burst mode starting from a first word identified by a word address.
Claim 20
Dependent Claim
98 words
A memory device comprising: a matrix of non-volatile multilevel memory cells grouped into pages to each of which a block of control information is associated; a plurality of reading elements for reading a plurality of pages in parallel; a decoding structure for selectively connecting each reading element to a plurality of memory cells, and for selectively connecting each memory cell to the plurality of reading elements; and an output circuit connected to said decoder structure for outputting a plurality of words of read pages in a burst mode starting from a first word identified by a word address.
Claim 21
Dependent Claim
77 words
The memory device according to claim 17 wherein said decoding structure comprises a plurality of selection elements grouped into blocks each organized into a tree with a plurality of levels, the tree having a root connected to a corresponding reading element and a last level connected to corresponding memory cells, and wherein at least one level starting from the last level is shared in a set formed by a plurality of trees associated with different reading elements.
Claim 22
Dependent Claim
37 words
The memory device according to claim 18 wherein each tree further includes an intermediate level directly connected to the at least one shared level, the intermediate level being partially shared among the trees of a corresponding set.
Claim 23
Dependent Claim
79 words
The memory device according to claim 19 wherein each level includes a set of branches for each branch of an immediately higher level, wherein the intermediate level has each set of branches with an exception of a first set of branches that is shared among the trees of the corresponding set of branches, and wherein the branches of the first set are connected in a staggered way to corresponding sets of branches of the at least one shared level.
Claim 24
Dependent Claim
58 words
The memory device according to claim 20 wherein said decoder structure comprises a first decoder circuit for generating a plurality of first selection signals each one for simultaneously controlling a corresponding selection element in each tree, and wherein corresponding selection elements in each non-shared level of the trees of each set are controlled by different first selection signals.
Claim 25
Dependent Claim
52 words
The memory device according to claim 21 wherein the first selection signals associated with each non-shared level are ordered according to a circular list, and wherein the corresponding selection elements in each non-shared level of the trees of each set are controlled by adjacent first selection signals according to the circular list.
Claim 26
Dependent Claim
96 words
The memory device according to claim 22 wherein each page includes a plurality of words, wherein said decoder structure further comprises a second decoder circuit for generating a plurality of second selection signals each one for controlling outputting of a correspondent word of read pages, and wherein the first decoder circuit is controlled by a first portion of a word address formed by a plurality of bits and the second decoder circuit is controlled by a value obtained by adding at least one bit having a preset value to a second portion of the word address.
Claim 27
Independent Claim
73 words
A method for reading a memory device comprising a matrix of memory cells grouped into pages to each of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel, the method comprising: using a decoding structure for selectively connecting each reading element to a plurality of memory cells, and for selectively connecting each memory cell to a plurality of reading elements.
Claim 28
Independent Claim
73 words
A method for reading a memory device comprising a matrix of memory cells grouped into pages to each of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel, the method comprising: using a decoding structure for selectively connecting each reading element to a plurality of memory cells, and for selectively connecting each memory cell to a plurality of reading elements.
Claim 29
Dependent Claim
76 words
The method according to claim 24 wherein the decoding structure comprises a plurality of selection elements grouped into blocks each organized into a tree with a plurality of levels, the tree having a root connected to a corresponding reading element and a last level connected to corresponding memory cells, and wherein at least one level starting from the last level is shared in a set formed by a plurality of trees associated with different reading elements.
Claim 30
Dependent Claim
36 words
The method according to claim 25 wherein each tree further includes an intermediate level directly connected to the at least one shared level, the intermediate level being partially shared among the trees of a corresponding set.
Claim 31
Dependent Claim
78 words
The method according to claim 26 wherein each level includes a set of branches for each branch of an immediately higher level, wherein the intermediate level has each set of branches with an exception of a first set of branches that is shared among the trees of the corresponding set of branches, and wherein the branches of the first set are connected in a staggered way to corresponding sets of branches of the at least one shared level.
Claim 32
Dependent Claim
57 words
The method according to claim 27 wherein the decoder structure comprises a first decoder circuit for generating a plurality of first selection signals each one for simultaneously controlling a corresponding selection element in each tree, and wherein corresponding selection elements in each non-shared level of the trees of each set are controlled by different first selection signals.
Claim 33
Dependent Claim
51 words
The method according to claim 28 wherein the first selection signals associated with each non-shared level are ordered according to a circular list, and wherein the corresponding selection elements in each non-shared level of the trees of each set are controlled by adjacent first selection signals according to the circular list.
Claim 34
Dependent Claim
95 words
The method according to claim 29 wherein each page includes a plurality of words, wherein said decoder structure further comprises a second decoder circuit for generating a plurality of second selection signals each one for controlling outputting of a correspondent word of read pages, and wherein the first decoder circuit is controlled by a first portion of a word address formed by a plurality of bits and the second decoder circuit is controlled by a value obtained by adding at least one bit having a preset value to a second portion of the word address.
Claim 35
Dependent Claim
31 words
The method according to claim 30 further comprising outputting a plurality of words of the read pages in a burst mode starting from a first word identified by a word address.
Claim 36
Dependent Claim
18 words
The method according to claim 24 wherein each of the memory cells comprises a non-volatile multilevel memory cell.
References Cited (Backward Citations)
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