Patent DE894082C successfully refreshed from Google Patents.
EP0905705A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Space-efficient semiconductor memory having hierarchical column select line architecture
Assignee: Infineon Technologies AG
•
Filing: 1998-07-30
•
Granted: —
•
Expires: 2018-07-30
Abstract
Abstract Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa, MAb), and having a space efficient layout. Chip size is kept small by employing a single column decoder (44) for different banks, and a hierarchical column select line architecture, with bit line switches (59, 61, 63, 65) of different columns having a shared active area such as a common source region. In an illustrative embodiment, global column select lines (GCSL 1 -GCSL (N/K) ) selectively activate global bit line switches (67, 68) which are coupled to bank-specific data lines (LDQ, LDQ ). Several bank bit line switches (59-66) are coupled to each global bit line switch, with two or more bank bit line switches of different columns having a shared diffusion region to realize a compact layout.
Inventors
- 👤 Gerhard Mueller
- 👤 Heinz Hoenigschmid
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 19:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C8/00; G11C8/10; G11C11/408; G11C11/4087
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
193 words
A semiconductor memory, comprising: a plurality of memory cell banks, each having a
plurality of rows and a plurality of columns, with bit
lines running in the respective columns to access memory
cells therein; a column decoder operative to selectively activate
at least one of a plurality of global column select lines
in accordance with a column address, each global column
select line controlling at least one global bit line
switch of a memory cell bank, each global bit line switch
coupled to a data line for the associated memory cell
bank; a plurality of bank bit line switches coupled to
each global bit line switch, with each bank bit line
switch coupled to a bit line of an associated column; said bit lines being selectively activated in
accordance with said column address such that a bit line
of a particular column is activated when both a global
bit line switch and a bank bit line switch associated
with that column are activated; wherein at least one said bank bit line switch has a
shared diffusion region with at least one of another bank
bit line switch or a global bit line switch.
Claim 2
Dependent Claim
54 words
The semiconductor memory of claim 1, wherein
each column includes a true bank bit line switch coupled
to a true bit line and a complementary bank bit line
switch coupled to a complementary bit line, and at least
four bank bit line switches and one global bit line
switch have a shared diffusion region.
Claim 3
Dependent Claim
33 words
The semiconductor memory of claim 2, wherein at
least four bank bit line switches coupled to true bit
lines of different columns and one global bit line switch
have a shared diffusion region.
Claim 4
Dependent Claim
42 words
The semiconductor memory of claim 2 wherein said
bank and global bit line switches are field effect
transistors and said diffusion region comprises a source
region for said bank bit line switches and a drain region
for said global bit line switches.
Claim 5
Dependent Claim
15 words
The semiconductor memory of claim 1 wherein said
memory comprises a dynamic random access memory.
Claim 6
Dependent Claim
27 words
The semiconductor memory of claim 1 wherein the
number of bank column select lines for each bank equals
N/K, where K is an integer greater than one.
Claim 7
Dependent Claim
44 words
The semiconductor memory of claim 1 wherein the
bank bit line switches are coupled to respective sense
amplifiers each connected to bit lines on both sides of
the sense amplifier in a shared configuration, the bit
lines arranged in a folded bit line configuration.
Claim 8
Dependent Claim
33 words
The semiconductor memory of claim 1 wherein the
bank bit line switches are coupled to respective sense
amplifiers each connected to bit lines on both sides
thereof in an open bit line arrangement.
Claim 9
Dependent Claim
121 words
The semiconductor memory of claim 1 wherein: bank bit line switches coupled to bit lines of
different columns and one global bit line switch have a
shared diffusion region; said shared diffusion region of said bank bit line
switches and said one global bit line switch is a
centralized shared diffusion region of a larger active
area; and said global and bank bit line switches each include
a gate conductor having an L-shaped portion, such that
the gate conductors of the bank bit line switches of
different columns and the one global bit line switch
separate said centralized region from one of a source or
drain region of each respective bank bit line switch and
the one global bit line switch.
Claim 10
Dependent Claim
18 words
The semiconductor memory of claim 9 wherein
four bank bit line switches share said centralized shared
diffusion region.
Claim 11
Dependent Claim
145 words
The semiconductor memory of claim 9, wherein
said bank bit line switches comprise true bank bit line
switches and complementary bank bit line switches, said
true and complementary bank bit line switches being
arranged in bank bit line switch sets such that the true
bank bit line switches of a given set are coupled to a
true global bit line switch associated with the given set
and the complementary bank bit line switches of the given
set are coupled to a complementary global bit line switch
associated with the given set; and the true bank bit line switches of the given set and
the associated true global bit line switch share a first
said centralized shared diffusion region, and the
complementary bank bit line switches of the given set and
the associated complementary global bit line switch share
a second said centralized shared diffusion region.
Claim 12
Dependent Claim
37 words
The semiconductor memory of claim 11 wherein a
gate conductor of at least one true bank bit line switch
or the given set is shared with a gate conductor of a
corresponding complementary bank bit line switch.
Claim 13
Dependent Claim
41 words
The semiconductor memory of claim 12 wherein
the gate conductor shared between the true bank bit line
switch and the complementary bank bit line switch of the
given set is U-shaped and extends between the first and
second centralized diffusion regions.
Claim 14
Dependent Claim
203 words
A semiconductor memory, comprising: a plurality of memory cell banks, each having a
plurality of rows and a plurality N of columns, with bit
lines running in the respective columns to access memory
cells therein; a column decoder operative to activate one of N/K
global column select lines in accordance with a column
address, where K is an integer greater than one, each
global column select line controlling at least a pair of
global bit line switches of a memory cell bank, each
global bit line switch coupled to a data line for the
associated memory cell bank; each memory cell bank including plural bank column
select lines, each coupled to bank bit line switches of
different columns and controlling switching states
thereof, with a set of bank bit line switches being
coupled to each global bit line switch; a bank column select decoder for each bank, coupled
to said bank column select lines, for selectively
activating said bank column select lanes in accordance
with said column address to thereby select, in
conjunction with an activated global column select line,
a particular column for memory cell access; wherein at least two bank bit line switches
associated with different columns share a diffusion
region.
Claim 15
Dependent Claim
28 words
The semiconductor memory of claim 14 wherein
four local bit line switches of different columns and at
least one global bit line switch have a shared diffusion
region.
Claim 16
Dependent Claim
15 words
The semiconductor memory of claim 14 wherein
the memory comprises a dynamic random access memory.
Claim 17
Dependent Claim
15 words
The semiconductor memory of claim 14 wherein
each memory cell bank includes folded bit lines.
Claim 18
Dependent Claim
15 words
The semiconductor memory of claim 14 wherein
each memory cell bank includes open bit lines.
Claim 19
Dependent Claim
303 words
A semiconductor memory, comprising: a plurality of memory cell banks, each having a
plurality of rows and a plurality N of columns, with bit
lines running in the respective columns to access memory
cells therein; a column decoder operative to activate one of N/K
global column select lines in accordance with a column
address, where K is an integer greater than one, each
global column select line controlling at least a pair of
global bit line switches of a memory cell bank, each
global bit line switch coupled to a data line for the
associated memory cell bank; each memory cell bank including plural bank column
select lines, each coupled to bank bit lane switches of
different columns and controlling switching states
thereof, with a set of bank bit line switches being
coupled to each global bit line switch; a bank column select decoder for each bank, coupled
to said bank column select lines, for selectively
activating said bank column select lines in accordance
with said column address to thereby select, in
conjunction with an activated global column select line,
a particular column for memory cell access; wherein: bank bit line switches coupled to bit lines of
different columns and an associated global bit line
switch have a shared diffusion region; said shared diffusion region of said bank bit line
switches and said associated global bit line switch is a
centralized shared diffusion region of a larger active
area; and, said global and bank bit line switches each include
a gate conductor having an L-shaped portion, such that
the gate conductors of the bank bit line switches of
different columns and the associated global bit line
switch separate said centralized region from one of a
source or drain region of each respective bank bit line
switch and the associated global bit line switch.
Claim 20
Dependent Claim
175 words
The semiconductor memory of claim 19, wherein
said bank bit line switches comprise true bank bit line
switches and complementary bank bit line switches, said
true and complementary bank bit line switches being
arranged in bank bit line switch sets such that the true
bank bit line switches of a given set are coupled to a
true global bit line switch associated with the given set
and the complementary bank bit line switches of the given
set are coupled to a complementary global bit line switch
associated with the given set; the true bank bit line switches of the given set and
the associated true global bit line switch share a first
said centralized shared diffusion region, and the
complementary bank bit line switches of the given set and
the associated complementary global bit line switch share
a second said centralized shared diffusion region; wherein a gate conductor for at least one true bank
bit line switch of the given set is shared with a gate
conductor of a corresponding complementary bank bit line
switch.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.