US6876596B1
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Decoder circuit with function of plural series bit line selection
Assignee: Halo LSI Inc
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Filing: 2003-11-07
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Granted: 2005-04-05
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Expires: 2023-11-07
Abstract
Abstract A bit line decoding circuit for accessing an array of two-bit memory cells. Two adjacent memory cells can be accessed by applying appropriate voltages to the terminals of the cells. A bit line decoder selects plural bit lines in the memory array and provides paths to apply or receive the voltages to or from the selected bit lines. In one embodiment, shared control gates of pass transistors which function as the bit line selection in a bit line deocder provides reduction in the number of control signals. Functions of applying a voltage for neighbor effect reduction and of providing a path for a reference voltage are also implemented in further embodiments.
Inventors
- 👤 Masaharu Kirihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:32
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/04; G11C16/0466; G11C16/0475
Claims Analysis
Total Claims: 70
Claim 1
Independent Claim
189 words
A bit line decoding circuit for accessing an array of two-bit memory cells comprising, a first stage containing pass gates whose first nodes are connected to sixteen bi-directional bit lines, whose second nodes are connected to bi-directional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 0 and 1 , 2 and 3 , 4 and 5 , 6 and 7 , 8 and 9 , 10 and 11 , 12 and 13 , and 14 and 15 , a second stage containing pass gates whose first nodes are connected to said bi-directional bit intermediate nodes, whose second nodes are connected to bi-directional sense driver lines, and whose third nodes are connected to second stage control signals, and bi-directional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 2
Dependent Claim
189 words
A bit line decoding circuit for accessing an array of two-bit memory cells comprising, a first stage containing pass gates whose first nodes are connected to sixteen bi-directional bit lines, whose second nodes are connected to bi-directional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 0 and 1 , 2 and 3 , 4 and 5 , 6 and 7 , 8 and 9 , 10 and 11 , 12 and 13 , and 14 and 15 , a second stage containing pass gates whose first nodes are connected to said bi-directional bit intermediate nodes, whose second nodes are connected to bi-directional sense driver lines, and whose third nodes are connected to second stage control signals, and bi-directional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 3
Dependent Claim
62 words
The bit line decoding circuit of claim 1 where in said first stage pass gates are comprised of N metal oxide semiconductor NMOS or P metal oxide semiconductor PMOS field effect transistors FETs whose drains are connected to said bi-directional bit lines, whose sources are connected to said bi-directional intermediate nodes and whose gates are connected to said first stage control signals.
Claim 4
Dependent Claim
28 words
The bit line decoding circuit of claim 1 wherein every fourth bit of said sixteen bi-directional intermediate nodes are connected together to form four separate intermediate junction nodes.
Claim 5
Dependent Claim
60 words
The bit line decoding circuit of claim 3 wherein said second stage pass gates are comprised of NMOS or PMOS FETs whose drains are connected to said intermediate junction nodes, whose every four sources are connected together to form bi-directional sense/driver nodes which connect to said bi-directional sense/driver circuits, and whose gates are connected to said second stage control signals.
Claim 6
Dependent Claim
40 words
The bit line decoding circuit of claim 4 wherein said first group of said four sources which are connected in common are connected to a bi-directional sense/driver circuit which drives the bit line left data of said two-bit memory cells.
Claim 7
Dependent Claim
40 words
The bit line decoding circuit of claim 4 wherein said second group of said four sources which are connected in common are connected to a bi-directional sense/driver circuit which drives the bit line common data of said two-bit memory cells.
Claim 8
Dependent Claim
40 words
The bit line decoding circuit of claim 4 wherein said third group of said four sources which are connected in common are connected to a bi-directional sense/driver circuit which drives the bit line right data of said two-bit memory cells.
Claim 9
Dependent Claim
49 words
The bit line decoding circuit of claim 1 wherein said bit line left data bi-directional sense/driver signal is combined as input to a selection switch with a bi-directional sense/driver left edge line wherein an edge left control signal's one or zero logic level selects between said two switch inputs.
Claim 10
Dependent Claim
58 words
The bit line decoding circuit of claim 1 wherein said bit line left data bi-directional sense/driver signal is combined as input to a selection switch with a bit line left data bi-directional sense/driver from an adjacent group of sixteen bit lines wherein said edge left control signal's one or zero logic level selects between said two switch inputs.
Claim 11
Dependent Claim
49 words
The bit line decoding circuit of claim 1 wherein said bit line right data bi-directional sense/driver signal is combined as input to a selection switch with a bi-directional sense/driver right edge line wherein an edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 12
Dependent Claim
58 words
The bit line decoding circuit of claim 1 wherein said bit line right data bi-directional sense/driver signal is combined as input to a selection switch with a bit line right data bi-directional sense/driver from an adjacent group of sixteen bit lines wherein said edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 13
Dependent Claim
255 words
A bit line decoding circuit for accessing an array of two-bit memory cells comprising, a first stage containing pass gates whose first nodes are connected to sixteen bi-directional bit lines, whose second nodes are connected to a first set of: bi-directional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive two pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 0 and 1 , 2 and 3 , 4 and 5 , 6 and 7 , 8 and 9 , 10 and 11 , 12 and 13 , and 14 and 15 , a second stage containing pass gates whose first nodes are connected to said first set of bi-directional intermediate nodes, whose second nodes are connected to a second set of bi-directional intermediate nodes, and whose third nodes are connected to second stage control signals, wherein said control signals drive four or more bits of said second stage pass gates, a third stage containing pass gates whose first nodes are connected to said second set of bi-directional bit intermediate nodes, whose second nodes are connected to bi-directional sense driver lines, and whose third nodes are connected to third stage control signals, and bi-directional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 14
Dependent Claim
255 words
A bit line decoding circuit for accessing an array of two-bit memory cells comprising, a first stage containing pass gates whose first nodes are connected to sixteen bi-directional bit lines, whose second nodes are connected to a first set of: bi-directional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive two pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 0 and 1 , 2 and 3 , 4 and 5 , 6 and 7 , 8 and 9 , 10 and 11 , 12 and 13 , and 14 and 15 , a second stage containing pass gates whose first nodes are connected to said first set of bi-directional intermediate nodes, whose second nodes are connected to a second set of bi-directional intermediate nodes, and whose third nodes are connected to second stage control signals, wherein said control signals drive four or more bits of said second stage pass gates, a third stage containing pass gates whose first nodes are connected to said second set of bi-directional bit intermediate nodes, whose second nodes are connected to bi-directional sense driver lines, and whose third nodes are connected to third stage control signals, and bi-directional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 15
Dependent Claim
62 words
The bit line decoding circuit of claim 12 where in said first stage pass gates are comprised of N metal oxide semiconductor NMOS or P metal oxide semiconductor PMOS field effect transistors FETs whose drains are connected to said bi-directional bit lines, whose sources are connected to said bi-directional intermediate nodes and whose gates are connected to said first stage control signals.
Claim 16
Dependent Claim
68 words
The bit line decoding circuit of claim 12 where in said second stage pass gates are comprised of N metal oxide semiconductor NMOS or P metal oxide semiconductor PMOS field effect transistors FETs whose drains are connected to said first set of bi-directional intermediate nodes, whose sources are connected to said second set of bi-directional intermediate nodes and whose gates are connected to said second stage control signals.
Claim 17
Dependent Claim
28 words
The bit line decoding circuit of claim 12 wherein every fourth bit of said sixteen bi-directional intermediate nodes are connected together to form four separate intermediate junction nodes.
Claim 18
Dependent Claim
60 words
The bit line decoding circuit of claim 15 wherein said second stage pass gates are comprised of NMOS or PMOS FETs whose drains are connected to said intermediate junction nodes, whose every four sources are connected together to form bi-directional sense/driver nodes which connect to said bi-directional sense/driver circuits, and whose gates are connected to said second stage control signals.
Claim 19
Dependent Claim
40 words
The bit line decoding circuit of claim 16 wherein said first group of said four sources which are connected in common are connected to a bi-directional sense/driver circuit which drives the bit line left data of said two-bit memory cells.
Claim 20
Dependent Claim
40 words
The bit line decoding circuit of claim 16 wherein said second group of said four sources which are connected in common are connected to a bi-directional sense/driver circuit which drives the bit line common data of said two-bit memory cells.
Claim 21
Dependent Claim
40 words
The bit line decoding circuit of claim 16 wherein said third group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line right data of said two-bit memory cells.
Claim 22
Dependent Claim
49 words
The bit line decoding circuit of claim 12 wherein said bit line left data bidirectional sense/driver signal is combined as input to a selection switch with a bidirectional sense/driver left edge line wherein an edge left control signal's one or zero logic level selects between said two switch inputs.
Claim 23
Dependent Claim
58 words
The bit line decoding circuit of claim 12 wherein said bit line left data bi-directional sense/driver signal is combined as input to a selection switch with a bit line left data bidirectional sense/driver from an adjacent group of sixteen bit lines wherein said edge left control signal's one or zero logic level selects between said two switch inputs.
Claim 24
Dependent Claim
49 words
The bit line decoding circuit of claim 12 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bidirectional sense/driver right edge line wherein an edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 25
Dependent Claim
58 words
The bit line decoding circuit of claim 12 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bit line right data bidirectional sense/driver from an adjacent group of sixteen bit lines wherein said edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 26
Dependent Claim
195 words
A bit line decoding circuit for accessing an array of two-bit memory cells comprising, a first stage containing pass gates whose first nodes are connected to sixteen bidirectional bit lines, whose second nodes are connected to bidirectional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 1 and 2 , 3 and 4 , 5 and 6 , 7 and 8 , 9 and 10 , 11 and 12 , 13 and 14 , and 15 and 0 (of next group of 16 bit lines), a second stage containing pass gates whose first nodes are connected to said bidirectional bit intermediate nodes, whose second nodes are connected to bidirectional sense driver lines, and whose third nodes are connected to second stage control signals, and bidirectional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 27
Dependent Claim
195 words
A bit line decoding circuit for accessing an array of two-bit memory cells comprising, a first stage containing pass gates whose first nodes are connected to sixteen bidirectional bit lines, whose second nodes are connected to bidirectional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 1 and 2 , 3 and 4 , 5 and 6 , 7 and 8 , 9 and 10 , 11 and 12 , 13 and 14 , and 15 and 0 (of next group of 16 bit lines), a second stage containing pass gates whose first nodes are connected to said bidirectional bit intermediate nodes, whose second nodes are connected to bidirectional sense driver lines, and whose third nodes are connected to second stage control signals, and bidirectional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 28
Dependent Claim
62 words
The bit line decoding circuit of claim 24 where in said first stage pass gates are comprised of N metal oxide semiconductor NMOS or P metal oxide semiconductor PMOS field effect transistors FETs whose drains are connected to said bidirectional bit lines, whose sources are connected to said bidirectional intermediate nodes and whose gates are connected to said first stage control signals.
Claim 29
Dependent Claim
28 words
The bit line decoding circuit of claim 24 wherein every fourth bit of said sixteen bidirectional intermediate nodes are connected together to form four separate intermediate junction nodes.
Claim 30
Dependent Claim
60 words
The bit line decoding circuit of claim 26 wherein said second stage pass gates are comprised of NMOS or PMOS FETs whose drains are connected to said intermediate junction nodes, whose every four sources are connected together to form bidirectional sense/driver nodes which connect to said bidirectional sense/driver circuits, and whose gates are connected to said second stage control signals.
Claim 31
Dependent Claim
40 words
The bit line decoding circuit of claim 27 wherein said first group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line left data of said two-bit memory cells.
Claim 32
Dependent Claim
40 words
The bit line decoding circuit of claim 27 wherein said second group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line common data of said two-bit memory cells.
Claim 33
Dependent Claim
40 words
The bit line decoding circuit of claim 27 wherein said third group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line right data of said two-bit memory cells.
Claim 34
Dependent Claim
49 words
The bit line decoding circuit of claim 24 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bidirectional sense/driver right edge line wherein an edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 35
Dependent Claim
58 words
The bit line decoding circuit of claim 24 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bit line right data bidirectional sense/drive from an adjacent group of sixteen bit lines wherein said edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 36
Independent Claim
196 words
A method of decoding bit lines for accessing an array of two-bit memory cells comprising the steps of: providing a first stage containing pass gates whose first nodes are connected to sixteen bidirectional bit lines, whose second nodes are connected to bidirectional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 0 and 1 , 2 and 3 , 4 and 5 , 6 and 7 , 8 and 9 , 10 and 11 , 12 and 13 , and 14 and 15 , providing a second stage containing pass gates whose first nodes are connected to said bidirectional bit intermediate nodes, whose second nodes are connected to bidirectional sense driver lines, and whose third nodes are connected to second stage control signals, and providing bidirectional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 37
Independent Claim
196 words
A method of decoding bit lines for accessing an array of two-bit memory cells comprising the steps of: providing a first stage containing pass gates whose first nodes are connected to sixteen bidirectional bit lines, whose second nodes are connected to bidirectional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 0 and 1 , 2 and 3 , 4 and 5 , 6 and 7 , 8 and 9 , 10 and 11 , 12 and 13 , and 14 and 15 , providing a second stage containing pass gates whose first nodes are connected to said bidirectional bit intermediate nodes, whose second nodes are connected to bidirectional sense driver lines, and whose third nodes are connected to second stage control signals, and providing bidirectional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 38
Dependent Claim
62 words
The method of decoding bit lines of claim 33 wherein said first stage pass gates are comprised of N metal oxide semiconductor NMOS or P metal oxide semiconductor PMOS field effect transistors FETs whose drains are connected to said bidirectional bit lines, whose sources are connected to said bidirectional intermediate nodes and whose gates are connected to said first stage control signals.
Claim 39
Dependent Claim
29 words
The method of decoding bit lines of claim 33 wherein every fourth bit of said sixteen bidirectional intermediate nodes are connected together to form four separate intermediate junction nodes.
Claim 40
Dependent Claim
61 words
The method of decoding bit lines of claim 35 wherein said second stage pass gates are comprised of NMOS or PMOS FETs whose drains are connected to said intermediate junction nodes, whose every four sources are connected together to form bidirectional sense/driver nodes which connect to said bidirectional sense/driver circuits, and whose gates are connected to said second stage control signals.
Claim 41
Dependent Claim
41 words
The method of decoding bit lines of claim 36 wherein said first group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line left data of said two-bit memory cells.
Claim 42
Dependent Claim
41 words
The method of decoding bit lines of claim 36 wherein said second group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line common data of said two-bit memory cells.
Claim 43
Dependent Claim
41 words
The method of decoding bit lines of claim 36 wherein said third group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line right data of said two-bit memory cells.
Claim 44
Dependent Claim
50 words
The method of decoding bit lines of claim 33 wherein said bit line left data bidirectional sense/driver signal is combined as input to a selection switch with a bidirectional sense/driver left edge line wherein an edge left control signal's one or zero logic level selects between said two switch inputs.
Claim 45
Dependent Claim
59 words
The method of decoding bit lines of claim 33 wherein said bit line left data bidirectional sense/driver signal is combined as input to a selection switch with a bit line left data bidirectional sense/driver from an adjacent group of sixteen bit lines wherein said edge left control signal's one or zero logic level selects between said two switch inputs.
Claim 46
Dependent Claim
50 words
The method of decoding bit lines of claim 33 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bidirectional sense/driver right edge line wherein an edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 47
Dependent Claim
59 words
The method of decoding bit lines of claim 33 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bit line right data bidirectional sense/driver from an adjacent group of sixteen bit lines wherein said edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 48
Independent Claim
263 words
A method of decoding bit lines for accessing an array of two-bit memory cells comprising the steps of: providing a first stage containing pass gates whose first nodes are connected to sixteen bidirectional bit lines, whose second nodes are connected to a first set of bidirectional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive two pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 0 and 1 , 2 and 3 , 4 and 5 , 6 and 7 , 8 and 9 , 10 and 11 , 12 and 13 , and 14 and 15 , providing a second stage containing pass gates whose first nodes are connected to said first set of bidirectional intermediate nodes, whose second nodes are connected to a second set of bidirectional intermediate nodes, and whos third nodes are connected to second stage control signals, wherein said control signals drive four or more bits of said second stage pass gates, providing a third stage containing pass gates whose first nodes are connected to said second set of bidirectional bit intermediate nodes, whose second nodes are connected to bidirectional sense driver lines, and whose third nodes are connected to third stage control signals, and providing bidirectional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 49
Independent Claim
263 words
A method of decoding bit lines for accessing an array of two-bit memory cells comprising the steps of: providing a first stage containing pass gates whose first nodes are connected to sixteen bidirectional bit lines, whose second nodes are connected to a first set of bidirectional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive two pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 0 and 1 , 2 and 3 , 4 and 5 , 6 and 7 , 8 and 9 , 10 and 11 , 12 and 13 , and 14 and 15 , providing a second stage containing pass gates whose first nodes are connected to said first set of bidirectional intermediate nodes, whose second nodes are connected to a second set of bidirectional intermediate nodes, and whos third nodes are connected to second stage control signals, wherein said control signals drive four or more bits of said second stage pass gates, providing a third stage containing pass gates whose first nodes are connected to said second set of bidirectional bit intermediate nodes, whose second nodes are connected to bidirectional sense driver lines, and whose third nodes are connected to third stage control signals, and providing bidirectional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 50
Dependent Claim
63 words
The method of decoding bit lines of claim 44 where in said first stage pass gates are comprised of N metal oxide semiconductor NMOS or P metal oxide semiconductor PMOS field effect transistors FETs whose drains are connected to said bidirectional bit lines, whose sources are connected to said bidirectional intermediate nodes and whose gates are connected to said first stage control signals.
Claim 51
Dependent Claim
69 words
The method of decoding bit lines of claim 44 where in said second stage pass gates are comprised of N metal oxide semiconductor NMOS or P metal oxide semiconductor PMOS field effect transistors FETs whose drains are connected to said first set of bidirectional intermediate nodes, whose sources are connected to said second set of bidirectional intermediate nodes and whose gates are connected to said second stage control signals.
Claim 52
Dependent Claim
29 words
The method of decoding bit lines of claim 44 wherein every fourth bit of said sixteen bidirectional intermediate nodes are connected together to form four separate intermediate junction nodes.
Claim 53
Dependent Claim
61 words
The method of decoding bit lines of claim 47 wherein said second stage pass gates are comprised of NMOS or PMOS FETs whose drains are connected to said intermediate junction nodes, whose every four sources are connected together to form bidirectional sense/driver nodes which connect to said bidirectional sense/driver circuits, and whose gates are connected to said second stage control signals.
Claim 54
Dependent Claim
41 words
The method of decoding bit lines of claim 48 wherein said first group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line left data of said two-bit memory cells.
Claim 55
Dependent Claim
41 words
The method of decoding bit lines of claim 48 wherein said second group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line common data of said two-bit memory cells.
Claim 56
Dependent Claim
41 words
The method of decoding bit lines of claim 48 wherein said third group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line right data of said two-bit memory cells.
Claim 57
Dependent Claim
50 words
The method of decoding bit lines of claim 44 wherein said bit line left data bidirectional sense/driver signal is combined as input to a selection switch with a bidirectional sense/driver left edge line wherein an edge left control signal's one or zero logic level selects between said two switch inputs.
Claim 58
Dependent Claim
59 words
The method of decoding bit lines of claim 44 wherein said bit line left data bidirectional sense/driver signal is combined as input to a selection switch with a bit line left data bidirectional sense/driver from an adjacent group of sixteen bit lines wherein said edge left control signal's one or zero logic level selects between said two switch inputs.
Claim 59
Dependent Claim
50 words
The method of decoding bit lines of claim 44 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bidirectional sense/driver right edge line wherein an edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 60
Dependent Claim
59 words
The method of decoding bit lines of claim 44 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bit line right data bidirectional sense/driver from an adjacent group of sixteen bit lines wherein said edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 61
Independent Claim
202 words
A method of decoding bit lines for accessing an array of two-bit memory cells comprising the steps of: providing a first stage containing pass gates whose first nodes are connected to sixteen bidirectional bit lines, whose second nodes are connected to bidirectional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 1 and 2 , 3 and 4 , 5 and 6 , 7 and 8 , 9 and 10 , 11 and 12 , 13 and 14 , and 15 and 0 (of next group of 16 bit lines), providing a second stage containing pass gates whose first nodes are connected to said bidirectional bit intermediate nodes, whose second nodes are connected to bidirectional sense driver lines, and whose third nodes are connected to second stage control signals, and providing bidirectional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 62
Independent Claim
202 words
A method of decoding bit lines for accessing an array of two-bit memory cells comprising the steps of: providing a first stage containing pass gates whose first nodes are connected to sixteen bidirectional bit lines, whose second nodes are connected to bidirectional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines 1 and 2 , 3 and 4 , 5 and 6 , 7 and 8 , 9 and 10 , 11 and 12 , 13 and 14 , and 15 and 0 (of next group of 16 bit lines), providing a second stage containing pass gates whose first nodes are connected to said bidirectional bit intermediate nodes, whose second nodes are connected to bidirectional sense driver lines, and whose third nodes are connected to second stage control signals, and providing bidirectional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.
Claim 63
Dependent Claim
63 words
The method of decoding bit lines of claim 56 where in said first stage pass gates are comprised of N metal oxide semiconductor NMOS or P metal oxide semiconductor PMOS field effect transistors FETs whose drains are connected to said bidirectional bit lines, whose sources are connected to said bidirectional intermediate nodes and whose gates are connected to said first stage control signals.
Claim 64
Dependent Claim
29 words
The method of decoding bit lines of claim 56 wherein every fourth bit of said sixteen bidirectional intermediate nodes are connected together to form four separate intermediate junction nodes.
Claim 65
Dependent Claim
61 words
The method of decoding bit lines of claim 58 wherein said second stage pass gates are comprised of NMOS or PMOS FETs whose drains are connected to said intermediate junction nodes, whose every four sources are connected together to form bidirectional sense/driver nodes which connect to said bidirectional sense/driver circuits, and whose gates are connected to said second stage control signals.
Claim 66
Dependent Claim
41 words
The method of decoding bit lines of claim 59 wherein said first group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line left data of said two-bit memory cells.
Claim 67
Dependent Claim
41 words
The method of decoding bit lines of claim 59 wherein said second group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line common data of said two-bit memory cells.
Claim 68
Dependent Claim
41 words
The method of decoding bit lines of claim 59 wherein said third group of said four sources which are connected in common are connected to a bidirectional sense/driver circuit which drives the bit line right data of said two-bit memory cells.
Claim 69
Dependent Claim
50 words
The method of decoding bit lines of claim 56 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bidirectional sense/driver right edge line wherein an edge right control signal's one or zero logic level selects between said two switch inputs.
Claim 70
Dependent Claim
59 words
The method of decoding bit lines of claim 56 wherein said bit line right data bidirectional sense/driver signal is combined as input to a selection switch with a bit line right data bidirectional sense/driver from an adjacent group of sixteen bit lines wherein said edge right control signal's one or zero logic level selects between said two switch inputs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 7.5 Years (Year 8) | 2012-04-04 | 2012-10-04 | 2013-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-04-04 | 2016-10-04 | 2017-04-05 | $7700.00 | Window Closed / Lapsed |