Patent US4503599A successfully refreshed from Google Patents.
US4503599A
Expired / Lapsed
US
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Method of fabricating field effect transistors
Assignee: Hitachi Ltd
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Filing: 1983-01-28
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Granted: 1985-03-12
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Expires: 2003-01-28
Abstract
Abstract Herein disclosed is a field effect transistor fabricating method comprising: the step of forming a surface portion of a semiconductor substrate with an impurity region for a channel; the step of forming a first material layer, which has a width substantially equal to that of a gate electrode, in such a position on said semiconductor substrate and is to be formed with said gate electrode, a second material layer, which has a width larger than that of said first material layer, above said first material layer, and source and drain regions by an ion implantation using said first and second material layers thus formed as a mask; the step of forming source and drain electrodes in contact with said source and drain regions; the step of forming a third material layer, which has a selectivity with said first material layer in its etched characteristics, on the semiconductor body thus far prepared by the foregoing steps; the step of forming at least an aperture by removing said first material layer in a state using said third material layer as a mask; and the step of forming said gate electrode in said aperture.
Inventors
- 👤 Kiichi Ueyanagi
- 👤 Susumu Takahashi
- 👤 Yasunari Umemoto
- 👤 Michiharu Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:47
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/061; H10D30/0612; H10D30/0614; H10D30/60; H10D30/791; H10D30/797; H10D30/80; H10D30/87; H10P; H10P76/00; H10P76/40; H10D62/00; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
275 words
A method of fabricating a field effect transistor, comprising: the step of forming a surface portion of a semiconductor substrate with an impurity region for a channel; the step of forming a first material layer above said semiconductor substrate; the step of forming at least a second material layer above said first material layer, which second material layer has a different composition from said first material layer; the step of forming a mask pattern required for formation of source and drain regions; the step of selectively removing the second material layer and then the first material layer through the mask pattern to form a first material pattern which has a width substantially equal to that of a gate electrode, in a position as is to be formed with said gate electrode, and to form a second material pattern above said first material pattern that has a width larger than that of said first material pattern; the step of removing said mask pattern; the step of forming source and drain regions by an ion implantation using said first and second material patterns as a mask; the step of annealing the semiconductor substrate at the positions where ion implantation has been performed; the step of forming source and drain electrodes in contact with said source and drain regions; the step of forming a third material layer, which has a selectivity with respect to said first material layer in its etching characteristics, on the semiconductor body thus far prepared by the foregoing steps; the step of forming at least an aperture by removing said first material pattern; and the step of forming said gate electrode in said aperture.
Claim 2
Independent Claim
275 words
A method of fabricating a field effect transistor, comprising: the step of forming a surface portion of a semiconductor substrate with an impurity region for a channel; the step of forming a first material layer above said semiconductor substrate; the step of forming at least a second material layer above said first material layer, which second material layer has a different composition from said first material layer; the step of forming a mask pattern required for formation of source and drain regions; the step of selectively removing the second material layer and then the first material layer through the mask pattern to form a first material pattern which has a width substantially equal to that of a gate electrode, in a position as is to be formed with said gate electrode, and to form a second material pattern above said first material pattern that has a width larger than that of said first material pattern; the step of removing said mask pattern; the step of forming source and drain regions by an ion implantation using said first and second material patterns as a mask; the step of annealing the semiconductor substrate at the positions where ion implantation has been performed; the step of forming source and drain electrodes in contact with said source and drain regions; the step of forming a third material layer, which has a selectivity with respect to said first material layer in its etching characteristics, on the semiconductor body thus far prepared by the foregoing steps; the step of forming at least an aperture by removing said first material pattern; and the step of forming said gate electrode in said aperture.
Claim 3
Dependent Claim
22 words
A field effect transistor fabricating method according to claim 1, wherein said second material layer is constructed of a plurality of sub-layers.
Claim 4
Dependent Claim
22 words
A field effect transistor fabricating method according to claim 1, wherein said third material layer is constructed of a plurality of sub-layers.
Claim 5
Dependent Claim
45 words
A field effect transistor fabricating method according to claim 3, wherein said third material layer is laminated of an inorganic material sub-layer, which has a selectivity with respect to said first material layer in its etching characteristics, and an organic high molecular weight material sub-layer.
Claim 6
Dependent Claim
39 words
A field effect transistor fabricating method according to claim 3, wherein said third material layer is constructed of an organic high-molecular weight material layer which has a selectivity with respect to said first material layer in its etching characteristics.
Claim 7
Dependent Claim
20 words
A field effect transistor fabricating method according to claim 1, wherein said semiconductor substrate is made of Group III-V material.
Claim 8
Dependent Claim
25 words
A field effect transistor fabricating method according to claim 1, wherein said third material layer acts as a mask in removing the first material pattern.
Claim 9
Dependent Claim
27 words
A field effect transistor fabricating method according to claim 1, wherein, prior to forming the first material layer, the semiconductor substrate is covered with a protective film.
Claim 10
Dependent Claim
36 words
A field effect transistor fabricating method according to claim 1, wherein the materials of said first material layer and the second material layer are resistant to heat at the temperature at which said annealing is performed.
Claim 11
Dependent Claim
59 words
A field effect transistor fabricating method according to claim 1, wherein the material of the first material layer is selected from the group consisting of Silicon Nitride, SiO 2 , polycrystalline silicon, Ti, Mo, TiSi 2 and MoSi 2 and the material of the second material layer is selected from the group consisting of SiO 2 and Silicon Nitride.
Claim 12
Dependent Claim
20 words
A field effect transistor fabricating method according to claim 10, wherein the third material layer includes a layer of photo-resist.
Claim 13
Dependent Claim
49 words
A field effect transistor fabricating method according to claim 10, wherein the third material layer includes at least one first sub-layer of a material selected from the group consisting of SiO 2 , polycrystalline silicon and Silicon Nitride, nitride, and at least one second sub-layer of a photo-resist material.
Claim 14
Independent Claim
319 words
A method of fabricating a field effect transistor, comprising: the step of forming a surface portion of a semiconductor substrate with an impurity region for a channel; the step of forming a first material layer above said semiconductor substrate; the step of forming at least a second material layer above said first material layer, which second material layer has a different composition from said first material layer; the step of forming a mask pattern required for formation of source and drain regions; the step of selectively removing the second material layer and then the first material layer through said mask pattern, to form a first material pattern which has a width substantially equal to that of a gate electrode, in a position in which said gate electrode is to be formed, and to form a second material pattern above said first material pattern that has a width larger than that of said first material pattern; the step of removing said mask pattern; the step of forming source and drain regions by an ion implantation using said first and second material patterns thus formed as a mask; the step of annealing the semiconductor substrate at the position where the ion implantation has been performed; the step of forming an inorganic insulating layer on the semiconductor body thus far prepared by the foregoing steps; the step of removing those regions of said inorganic insulating layer, which are to be formed with source and drain electrodes; the step of forming said source and drain electrodes in contact with said source and drain regions; the step of forming a third material layer, which has a selectivity with respect to said first material layer in its etching characteristics, on the semiconductor body thus far prepared by the foregoing steps; the step of forming at least an aperture by removing said first material layer; and the step of forming said gate electrode in said aperture.
Claim 15
Independent Claim
319 words
A method of fabricating a field effect transistor, comprising: the step of forming a surface portion of a semiconductor substrate with an impurity region for a channel; the step of forming a first material layer above said semiconductor substrate; the step of forming at least a second material layer above said first material layer, which second material layer has a different composition from said first material layer; the step of forming a mask pattern required for formation of source and drain regions; the step of selectively removing the second material layer and then the first material layer through said mask pattern, to form a first material pattern which has a width substantially equal to that of a gate electrode, in a position in which said gate electrode is to be formed, and to form a second material pattern above said first material pattern that has a width larger than that of said first material pattern; the step of removing said mask pattern; the step of forming source and drain regions by an ion implantation using said first and second material patterns thus formed as a mask; the step of annealing the semiconductor substrate at the position where the ion implantation has been performed; the step of forming an inorganic insulating layer on the semiconductor body thus far prepared by the foregoing steps; the step of removing those regions of said inorganic insulating layer, which are to be formed with source and drain electrodes; the step of forming said source and drain electrodes in contact with said source and drain regions; the step of forming a third material layer, which has a selectivity with respect to said first material layer in its etching characteristics, on the semiconductor body thus far prepared by the foregoing steps; the step of forming at least an aperture by removing said first material layer; and the step of forming said gate electrode in said aperture.
Claim 16
Dependent Claim
20 words
A field effect transistor fabricating method according to claim 13, wherein said semiconductor substrate is made of Group III-V material.
Claim 17
Dependent Claim
25 words
A field effect transistor fabricating method according to claim 13, wherein said third material layer acts as a mask in removing the first material pattern.
Claim 18
Dependent Claim
60 words
A field effect transistor fabricating method according to claim 13, wherein the material of the first material layer is selected from the group consisting of Silicon Nitride, SiO 2 , polycrystalline silicon, Ti, Mo, TiSi 2 and MoSi 2 , and the material of the second material layeer is selected from the group consisting of SiO 2 and Silicon Nitride.
Claim 19
Dependent Claim
20 words
A field effect transistor fabricating method according to claim 16, wherein the third material layer includes a layer of photo-resist.
Claim 20
Dependent Claim
48 words
A field effect transistor fabricating method according to claim 17, wherein the third material layer includes at least one first sub-layer of a material selected from the group consisting of SiO 2 , polycrystalline silicon and Silicon Nitride, and at least one second sub-layer of a photo-resist material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-11 | 1988-09-10 | 1989-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-11 | 1992-09-10 | 1993-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-11 | 1996-09-10 | 1997-03-12 | $7700.00 | Window Closed / Lapsed |