Metallization of selectively implanted AIII -BV compound semiconductors

Claim 2

Method for fabricating a semiconductor arrangement using phototechnique processes and a semiconductor body of an A III -B V compound, which comprises doping a semiconductor body of an A III -B V compound with a first doping substance in a concentration to produce non-barrier zones at parts of the surface of the semiconductor body, and with a second doping substance in a concentration to produce barrier zones at other parts of the semiconductor surface, and applying only one metallization to the surface to obtain barrier and non-barrier contacts on the different zones.

Claim 3

Method for fabricating a semiconductor arrangement with a semiinsulating substrate as a semiconductor body of an A III -B V compound, which comprises doping a semiconductor body of an A III -B V compound with different doping substances on different zones of the semiconductor body to form barrier and non-barrier zones, and applying only one metallization to the surface to obtain barrier and non-barrier contacts on the differend zones and wherein (a) at least one first conducting layer is placed by a local ion implantation with a dose of 10 12 to 10 14 atoms/cm 2 of one of the elements selected from the group consisting of Te, S, Se and Si on an exposed surface or a surface covered with a thin passivating layer of the substrate so that the first year contains 1×10 15 to 5×10 17 doping atoms/cm 3 , (b) at another place, placing at least one second conducting layer by local ion implantation with a dose of 10 14 to 10 17 atoms/cm 2 of the element Ge on an exposed surface, or a surface covered with a thin passivating layer of the substrate so that the second layer contains more than 10 18 doping atoms/cm 3 , and (c) depositing a single metal layer for preparing barrier and non-barrier contacts, barrier contacts being generated on the first layer and conducting contacts on the second layer.

Claim 4

Method for fabricating a semiconductor arrangement with a semiinsulating substrate as a semiconductor body of an A III -B V compound, which comprises doping a semiconductor body of an A III -B V compound with different doping substances on different zones of the semiconductor body to form barrier and non-barrier zones, and applying only one metallization to the surface to obtain barrier and non-barrier contacts on the differend zones and wherein (a) at least one first conducting layer is placed by a local ion implantation with a dose of 10 12 to 10 14 atoms/cm 2 of one of the elements selected from the group consisting of Te, S, Se and Si on an exposed surface or a surface covered with a thin passivating layer of the substrate so that the first year contains 1×10 15 to 5×10 17 doping atoms/cm 3 , (b) at another place, placing at least one second conducting layer by local ion implantation with a dose of 10 14 to 10 17 atoms/cm 2 of the element Ge on an exposed surface, or a surface covered with a thin passivating layer of the substrate so that the second layer contains more than 10 18 doping atoms/cm 3 , and (c) depositing a single metal layer for preparing barrier and non-barrier contacts, barrier contacts being generated on the first layer and conducting contacts on the second layer.

Claim 5

Method for fabricating semiconductor arrangement according to claim 2, wherein the semiconductor arrangement is a diode, a field-effect transistor or an integrated circuit composed of these elements and additional passive elements.

Claim 6

Method for fabricating a semiconductor arrangement with a semiconductor body of an A III -B V compound, which comprises doping a semiconductor body of an A III -B V compound with different doping substances on different zones of the semiconductor body to form barrier and non-barrier zones, and applying only one metallization to the surface to obtain barrier and non-barrier contacts on the different zones, wherein the semiconductor substrate with a doping concentration of more than 10 17 impurities/cm 3 , by (a) generating a surface layer 0.5 to 5 μm thick with 10 15 to 5×10 17 impurities/cm 3 by diffusion or ion implantation, (b) at another place, placing at least one conducting layer by local implantation with a dose of 10 14 to 10 17 atoms/cm 2 , of the element Ge on an exposed surface, or a surface covered with a thin passivating layer, of the semiconductor body, so that the layer contains more than 10 18 doping atoms/cm 3 , and (c) depositing a single metal layer for preparing barrier and non-barrier contacts, barrier contacts being generated on the surface layer and conducting contacts on the conducting layer.

Claim 7

Method for fabricating a semiconductor arrangement with a semiconductor body of an A III -B V compound, which comprises doping a semiconductor body of an A III -B V compound with different doping substances on different zones of the semiconductor body to form barrier and non-barrier zones, and applying only one metallization to the surface to obtain barrier and non-barrier contacts on the different zones, wherein the semiconductor substrate with a doping concentration of more than 10 17 impurities/cm 3 , by (a) generating a surface layer 0.5 to 5 μm thick with 10 15 to 5×10 17 impurities/cm 3 by diffusion or ion implantation, (b) at another place, placing at least one conducting layer by local implantation with a dose of 10 14 to 10 17 atoms/cm 2 , of the element Ge on an exposed surface, or a surface covered with a thin passivating layer, of the semiconductor body, so that the layer contains more than 10 18 doping atoms/cm 3 , and (c) depositing a single metal layer for preparing barrier and non-barrier contacts, barrier contacts being generated on the surface layer and conducting contacts on the conducting layer.

Claim 8

Method for fabricating a semiconductor arrangement according to claim 4, wherein the semiconductor arrangement is a beam lead Schottky diode.

Claim 9

Method according to claim 2 or claim 4, wherein the passivating layer is a silicon nitride layer about 0.05 μm thick.

Claim 10

Method according to claim 2 or claim 4, wherein the metal layer is a Cr/Au layer or a Cr/Au/W/Au layer.