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US4375600A
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Sense amplifier for integrated memory array
Assignee: International Business Machines Corp
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Filing: 1981-05-05
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Granted: 1983-03-01
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Expires: 2001-05-05
Abstract
Abstract A memory-array sense amplifier includes a grounded-gate depletion-mode FET connected between a bit line and a sense node. Another FET connects a supply voltage VDD to the sense node when turned on by a clock phase signal. Further FETs form a latch circuit.
Inventors
- 👤 Philip T. Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:20
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356026; H03K3/356052
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
126 words
In a memory array having a bit line connected to a set of storage cells, and having a source for producing at least one clock phase during a portion of a storage cycle of said memory array, a sense amplifier comprising: a depletion FET of a predetermined channel polarity and having a source coupled to said bit line, a drain coupled to a sense node, and a gate connected directly to a ground potential; and a further FET of the same predetermined channel polarity and having a source coupled to said sense node, a drain coupled to a compatible supply potential, and a gate connected to receive said one clock phase so as to switch said further FET both on and off during said storage cycle.
Claim 2
Dependent Claim
126 words
In a memory array having a bit line connected to a set of storage cells, and having a source for producing at least one clock phase during a portion of a storage cycle of said memory array, a sense amplifier comprising: a depletion FET of a predetermined channel polarity and having a source coupled to said bit line, a drain coupled to a sense node, and a gate connected directly to a ground potential; and a further FET of the same predetermined channel polarity and having a source coupled to said sense node, a drain coupled to a compatible supply potential, and a gate connected to receive said one clock phase so as to switch said further FET both on and off during said storage cycle.
Claim 3
Dependent Claim
14 words
The memory array of claim 1, wherein said second transistor is an enhancement-mode FET.
Claim 4
Dependent Claim
13 words
The memory array of claim 1, wherein said predetermined channel polarity is N-channel.
Claim 5
Dependent Claim
169 words
In a memory array having first and second bit lines connected to first and second sets of storage cells, and having a source for producing multiple clock phases during a storage cycle of said memory array, a sense amplifier comprising: first and second depletion FETs each of the same predetermined channel polarity and having a source connected to one of said bit lines, a drain connected to one of first and second sense nodes, and a gate connected directly to a ground potential; third and fourth FETs each of said same predetermined channel polarity and having a source connected to one of said sense nodes, a drain connected to a compatible supply potential, and a gate connected to a first of said clock phases; and fifth and sixth FETs each having a source connected to a second of said clock phases, a drain connected to one of said sense nodes, and a gate connected to an opposite one of said sense nodes so as to form a latch circuit.
Claim 6
Dependent Claim
169 words
In a memory array having first and second bit lines connected to first and second sets of storage cells, and having a source for producing multiple clock phases during a storage cycle of said memory array, a sense amplifier comprising: first and second depletion FETs each of the same predetermined channel polarity and having a source connected to one of said bit lines, a drain connected to one of first and second sense nodes, and a gate connected directly to a ground potential; third and fourth FETs each of said same predetermined channel polarity and having a source connected to one of said sense nodes, a drain connected to a compatible supply potential, and a gate connected to a first of said clock phases; and fifth and sixth FETs each having a source connected to a second of said clock phases, a drain connected to one of said sense nodes, and a gate connected to an opposite one of said sense nodes so as to form a latch circuit.
Claim 7
Dependent Claim
13 words
The memory array of claim 4, wherein said predetermined channel polarity is N-channel.
Claim 8
Dependent Claim
15 words
The memory array of claim 5, wherein said third and fourth FETs are enhancement FETs.
Claim 9
Dependent Claim
15 words
The memory array of claim 5, wherein said fifth and sixth FETs are enhancement FETs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-28 | 1986-08-30 | 1987-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-28 | 1990-08-30 | 1991-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-28 | 1994-08-30 | 1995-03-01 | $7700.00 | Window Closed / Lapsed |