Mos detector or sensing circuit

Claim 2

A circuit for detecting a voltage on an input node and providing a high level voltage change on a sense node, comprising: a transistor having a source-drain path connected in series between the input node and the sense node and having a gate; a gated capacitor separate from the inherent capacitance of the transistor connected between the gate of the transistor and the sense node, the gated capacitor switching from a very low capacitance mode to a high capacitance mode when the voltage across it exceeds a threshold value; means to apply a read clock pulse of a given voltage level to the gate of the transistor; the output on said sense node after said read clock pulse being two-valued, one value occurring when the voltage on the input node is no more than said threshold value different from said given voltage level and the other occurring when the voltage on the input node is more than said threshold value different from the given voltage level.

Claim 3

A circuit according to claim 1 wherein means are provided for precharging the input node to a voltage level not more than said threshold value different from said given voltage, prior to said read clock pulse.

Claim 4

A circuit according to claim 1 wherein the transistor is a P-channel MOS transistor and the gated capacitor has its gate electrode connected to the gate of the MOS transistor.

Claim 5

A circuit according to claim 3 wherein means are provided to precharge the input and sense nodes to said voltage prior to the read clock pulse.

Claim 6

A circuit for detecting a voltage on an input node and providing a high level voltage change on a sense node, comprising: a transistor having a source-drain path connected in series between the input node and the sense node and having a gate; a gated capacitor connected between the gate of the transistor and the sense node, the gated capacitor switching from a very low capacitance mode to a high capacitance mode when the voltage across it exceeds a threshold value; means to apply a read clock pulse of a given voltage level to the gate of the transistor; means to apply a two-valued signal to the input node one value being no more than said threshold value different from said given voltage level and the other being more than said threshold value different from the given voltage level, means for precharging the input node to a voltage level not more than said threshold value different from said given voltage, prior to said read clock pulse, and means for precharging the sense node to a voltage level the same as the input node, prior to the read clock pulse.

Claim 7

A circuit for detecting a voltage on an input node and providing a high level voltage change on a sense node, comprising: a transistor having a source-drain path connected in series between the input node and the sense node and having a gate; a gated capacitor connected between the gate of the transistor and the sense node, the gated capacitor switching from a very low capacitance mode to a high capacitance mode when the voltage across it exceeds a threshold value; means to apply a read clock pulse of a given voltage level to the gate of the transistor; means to apply a two-valued signal to the input node one value being no more than said threshold value different from said given voltage level and the other being more than said threshold value different from the given voltage level, means for precharging the input node to a voltage level not more than said threshold value different from said given voltage, prior to said read clock pulse, and means for precharging the sense node to a voltage level the same as the input node, prior to the read clock pulse.

Claim 8

A circuit according to claim 5 wherein the sense node exhibits a capacitance which is very small compared to capacitance exhibited by the gated capacitor in said high capacitance mode.

Claim 9

A sense circuit for a semiconductor memory of the type having an array of memory cells in rows and columns, comprising: an MOS transistor being a source-to-drain path and a gate; an input node connected to a column line of the array; a sense node connected to output circuitry; means connecting the source-to-drain path of the MOS transistor in series between the input node and the sense node; means applying a read pulse to the gate of the MOS transistor, the read pulse having a given voltage level and having leading and trailing edges; a capacitor separate from the inherent capacitance of the MOS transistor connected between the gate of the MOS transistor and the sense node, the capacitor exhibiting a low capacitance value when the voltage across it is below a threshold and exhibiting a high value when the voltage across it is more than said threshold; the trailing edge of the read pulse being coupled to the sense node by the capacitor when the voltage on the sense node differs from said given voltage level by at least said threshold, but not being significantly coupled to the sense node when the voltage on the sense node differs from said given voltage by less than said threshold.

Claim 10

A sense circuit for a semiconductor memory of the type having an array of memory cells in rows and columns, comprising: an MOS transistor being a source-to-drain path and a gate; an input node connected to a column line of the array; a sense node connected to output circuitry; means connecting the source-to-drain path of the MOS transistor in series between the input node and the sense node; means applying a read pulse to the gate of the MOS transistor, the read pulse having a given voltage level and having leading and trailing edges; a capacitor separate from the inherent capacitance of the MOS transistor connected between the gate of the MOS transistor and the sense node, the capacitor exhibiting a low capacitance value when the voltage across it is below a threshold and exhibiting a high value when the voltage across it is more than said threshold; the trailing edge of the read pulse being coupled to the sense node by the capacitor when the voltage on the sense node differs from said given voltage level by at least said threshold, but not being significantly coupled to the sense node when the voltage on the sense node differs from said given voltage by less than said threshold.

Claim 11

A circuit according to claim 7 including means for precharging the input node and the sense node prior to said leading edge to a voltage level which differs from said given voltage level by less than said threshold.

Claim 12

A circuit according to claim 7 wherein the capacitance of the sense node is much less than the capacitance of said capacitor.

Claim 13

An input circuit for an MOS/LSI semiconductor chip for detecting small voltage changes, comprising: an MOS transistor having a source-to-drain path and a gate; an input node connected to an input terminal of the semiconductor chip; a sense node connected to output circuitry; means connecting the source-to-drain path of the MOS transistor in series between the input node and the sense node; means applying a read pulse to the gate of the MOS transistor, the read pulse having a given voltage level and having leading and trailing edges; a capacitor separate from the inherent capacitance of the MOS transistor connected between the gate of the MOS transistor and the sense node, the capacitor exhibiting a low capacitance value when the voltage across it is below a threshold and exhibiting a high value when the voltage across it is more than said threshold; the trailing edge of the read pulse being coupled to the sense node by the capacitor when the voltage on the sense node differs from said given voltage level by at least said threshold, but not being significantly coupled to the sense node when the voltage on the sense node differs from said given voltage by less than said threshold.

Claim 14

An input circuit for an MOS/LSI semiconductor chip for detecting small voltage changes, comprising: an MOS transistor having a source-to-drain path and a gate; an input node connected to an input terminal of the semiconductor chip; a sense node connected to output circuitry; means connecting the source-to-drain path of the MOS transistor in series between the input node and the sense node; means applying a read pulse to the gate of the MOS transistor, the read pulse having a given voltage level and having leading and trailing edges; a capacitor separate from the inherent capacitance of the MOS transistor connected between the gate of the MOS transistor and the sense node, the capacitor exhibiting a low capacitance value when the voltage across it is below a threshold and exhibiting a high value when the voltage across it is more than said threshold; the trailing edge of the read pulse being coupled to the sense node by the capacitor when the voltage on the sense node differs from said given voltage level by at least said threshold, but not being significantly coupled to the sense node when the voltage on the sense node differs from said given voltage by less than said threshold.

Claim 15

A circuit according to claim 10 including means for precharging the input node and the sense node prior to said leading edge to a voltage level which differs from said given voltage level by less than said threshold.

Claim 16

A circuit according to claim 10 wherein the capacitance of the sense node is much less than the capacitance of said capacitor.