US3588848A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input-output control circuit for memory circuit
Assignee: United States Department of the Army
•
Filing: 1969-08-04
•
Granted: 1971-06-28
•
Expires: 1989-08-04
Abstract
Abstract A CONTROL CIRCUIT FOR MOS MEMORY CIRCUITS WHICH PROVIDES A LOW IMPEDANCE TO BIT LINES DURING THE "WRITE" CYCLE AND A HIGH IMPEDANCE DURING THE "READ" CYCLE SO THAT THE MEMORY CELL STATES WON''T BE CHANGED BY CONTROL CIRCUIT SIGNALS.
Inventors
- 👤 Herman W Van Beek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-27 | 1974-12-27 | 1975-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-27 | 1978-12-27 | 1979-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-27 | 1982-12-27 | 1983-06-28 | $7700.00 | Window Closed / Lapsed |