Self-isolating cross-coupled sense amplifier latch circuit

Claim 2

In an electronic memory system, a sense amplifier latching circuit comprising: first and second sources of potential; first and second input nodes; first and second output nodes; first and second transistors, each having first and second controlled electrodes and a control electrode, said first controlled electrodes being electrically connected, said second controlled electrode of said first transistor being electrically connected to the control electrode of said second transistor, said second controlled electrode of said second transistor being electrically connected to the control electrode of said first transistor; said first output node being in electrical contact with said electrical connection between the second controlled electrode of said first transistor and the control electrode of said second transistor; said second output node being in electrical contact with said electrical connection between said second controlled electrode of said second transistor and the control electrode of said first transistor; a first unidirectionally conducting means electrically connected between said first source of potential and said first output node; a second unidirectionally conducting means electrically connected between said first source of potential and said second output node; a third unidirectionally conducting means electrically connected between said first input node and said first output node; a fourth unidirectionally conducting means electrically connected between said second input node and said second output node; and a third transistor having first and second controlled electrodes and a control electrode, the first controlled electrode of said third transistor being electrically connected to said second source of potential, the second controlled electrode of said third transistor being in electrical contact with said electrical connection between the first controlled electrodes of said first and second transistors, the control electrode of said third transistor being electrically connected to a third source of potential.

Claim 3

A sense amplifier latching circuit as in claim 1 wherein said third source of potential is a variable source of potential.

Claim 4

A sense amplifier latching circuit as in claim 2 wherein said variable source of potential has two stable states.

Claim 5

A sense amplifier latching circuit as in claim 3 wherein said first and second sources of potential are fixed sources of potential.

Claim 6

A sense amplifier latching circuit as in claim 4 wherein a first one of the two stable states of said third source of potential approximates in value that of said first fixed source of potential while the second of the two stable states of said third source of potential approximates in value that of the second fixed source of potential.

Claim 7

A sense amplifier latching circuit as in claim 3 wherein the first stable state of said third source of potential biases said third transistor into its low impedance state, the second of said two stable states biasing said third transistor into its high impedance state.

Claim 8

A sense amplifier latching circuit as in claim 6 wherein a potential difference is applied to said first and second input nodes at a time when said third transistor is in its high impedance state.

Claim 9

A sense amplifier latching circuit as in claim 7 wherein said input signal causes one of said third and fourth unidirectionally conducting means to conduct thereby establishing a potential difference on the control electrodes of said first and second transistors such that when said third transistor is placed in its low impedance state, one of said first and second transistors conducts more current than the other until one of said first and second transistors is turned off and a potential difference between said first and second output nodes is established, said potential difference being approximately equal to the potential difference between said first and second fixed sources of potential.

Claim 10

A sense amplifier latching circuit as in claim 8 wherein said first and second input nodes are at a substantially equal potential level approximately equal to the value of the potential level of said first fixed source of potential prior to the application of an input signal.

Claim 11

A sense amplifier latching circuit as in claim 1 further comprising: a push pull amplifier having first and second input nodes, the first input node of said push pull amplifier being electrically coupled to the first output node, the second input node of said differential amplifier being electrically coupled to the second output node.

Claim 12

A sense amplifier latching circuit as in claim 1 wherein said first, second, and third transistors are field effect transistors.

Claim 13

A sense amplifier latching circuit as in claim 11 wherein said field effect transistors are enhancement mode field effect transistors.

Claim 14

A sense amplifier latching circuit as in claim 1 wherein said first and second unidirectionally conducting means comprise fourth and fifth field effect transistors, respectively, each having first and second controlled electrodes and a control electrode, said first controlled electrodes being electrically connected to said first source of potential, said second controlled electrode of said fourth field effect transistor being electrically connected to said first output node, said second controlled electrode of said fifth field effect transistor being electrically connected to said second output node.

Claim 15

A sense amplifier latching circuit as in claim 13 wherein said fourth and fifth field effect transistors are of the depletion mode type each having its control electrode electrically connected to its second controlled electrode, respectively.

Claim 16

A sense amplifier latching circuit as in claim 1 wherein said third and fourth unidirectionally conducting means comprise sixth and seventh field effect transistors each having first and second controlled electrodes and a control electrode.

Claim 17

A sense amplifier latching circuit as in claim 15 wherein said sixth and seventh field effect transistors are of the enhancement type each having an electrical connection between its second controlled electrode and its control electrode, respectively, said sixth field effect transistor having its first controlled electrode electrically connected to said first input node, said seventh field effect transistor having its first controlled electrode electrically connected to said second input node.

Claim 18

An array of semiconductor memory cells formed in a semiconductor substrate, said array comprising: a plurality of word lines arranged in parallel with each other each connected to a plurality of said cells arranged in a row; a plurality of bit lines, parallel to each other, arranged orthogonally to said word lines, a pair of said bit lines being operatively associated with each cell in a column of cells; a sense amplifier latching circuit as in claim 1 having its first input node electrically connected to a first one of said pair of said bit lines, and second input node connected to a second one of said pair of said bit lines.

Claim 19

An array of semiconductor memory cells as in claim 17 further comprising: means for bringing said first and second ones of said pair of bit lines to a potential level approximately equal to the potential of said first source of potential, said third and fourth unidirectionally conducting means being arranged to minimize current flow between said first and second bit lines and said first and second output nodes.

Claim 20

An array of semiconductor memory cells as in claim 18 further comprising: a push pull amplifier having first and second input nodes, the first input node of said push pull amplifier being electrically coupled to the first output node, the second input node of said differential amplifier being electrically coupled to the second input node.

Claim 21

An improved circuit comprising: first and second field effect transistors each having source, drain, and gate electrodes, said source electrodes being electrically connected, said drain electrode of said first field effect transistor being electrically connected to the gate electrode of said second field effect transistor, said drain electrode of said second field effect transistor being electrically connected to the gate electrode of said first field effect transistor; a third field effect transistor having a source, drain and gate electrode, the drain electrode of said third field effect transistor being electrically connected to said electrical connection between said source electrodes of said first and second field effect transistors, the gate electrode of said third field effect transistor being electrically connected to a pulsating source of potential; a fourth field effect transistor having a source, drain and gate electrode, having its drain electrode electrically connected to a first fixed source of potential, its gate and source electrodes being electrically coupled to each other and to the connection between the drain electrode of said first field effect transistor and the gate electrode of said second field effect transistor thereby providing a first output point; a fifth field effect transistor having a source, drain, and gate electrode, said drain electrode being electrically connected to said first fixed source of potential, the gate and source electrodes being electrically coupled to each other and to the electrical connection between the drain electrode of said second field effect transistor and the gate electrode of said first field effect transistor thereby providing a second output point; a sixth field effect transistor having a drain, source and gate electrodes, having its drain and gate electrodes coupled to each other and to said first output point, its source electrode being electrically connected to a first input point; a seventh field effect transistor having a drain, source and gate electrode, having its drain and gate electrodes coupled to each other and to said second output point, the source electrode of said seventh field effect transistor being coupled to a second input point; and the source electrode of said third field effect transistor being coupled to a second fixed source of potential.

Claim 22

An improved circuit comprising: first and second field effect transistors each having source, drain, and gate electrodes, said source electrodes being electrically connected, said drain electrode of said first field effect transistor being electrically connected to the gate electrode of said second field effect transistor, said drain electrode of said second field effect transistor being electrically connected to the gate electrode of said first field effect transistor; a third field effect transistor having a source, drain and gate electrode, the drain electrode of said third field effect transistor being electrically connected to said electrical connection between said source electrodes of said first and second field effect transistors, the gate electrode of said third field effect transistor being electrically connected to a pulsating source of potential; a fourth field effect transistor having a source, drain and gate electrode, having its drain electrode electrically connected to a first fixed source of potential, its gate and source electrodes being electrically coupled to each other and to the connection between the drain electrode of said first field effect transistor and the gate electrode of said second field effect transistor thereby providing a first output point; a fifth field effect transistor having a source, drain, and gate electrode, said drain electrode being electrically connected to said first fixed source of potential, the gate and source electrodes being electrically coupled to each other and to the electrical connection between the drain electrode of said second field effect transistor and the gate electrode of said first field effect transistor thereby providing a second output point; a sixth field effect transistor having a drain, source and gate electrodes, having its drain and gate electrodes coupled to each other and to said first output point, its source electrode being electrically connected to a first input point; a seventh field effect transistor having a drain, source and gate electrode, having its drain and gate electrodes coupled to each other and to said second output point, the source electrode of said seventh field effect transistor being coupled to a second input point; and the source electrode of said third field effect transistor being coupled to a second fixed source of potential.

Claim 23

An improved circuit as in claim 20 wherein said field effect transistors are of the N-channel type.

Claim 24

An improved circuit as in claim 21 wherein said first, second, third, sixth, and seventh field effect transistors are enhancement mode while said fourth and fifth field effect transistors are depletion mode.

Claim 25

An improved circuit as in claim 22 wherein said first fixed source of potential is positive relative to said second fixed source of potential and said pulsating source of potential has two stable states each of said stable states being approximately equal in potential level to one of said first and second fixed sources of potential.

Claim 26

An improved circuit as in claim 23 further comprising: means for bringing said first and second input points to a potential level approximately equal to the potential level of said first fixed source of potential, said fourth and fifth field effect transistors bringing said first and second output points to a potential level approximately equal to the potential level of said first fixed source of potential, such that when either input point receives a potential level less than that of said first fixed source of potential, the corresponding one of said sixth and seventh field effect transitors conduct thereby conditioning one of said first and second field effect transistors to a lesser gate to source bias level than the other, such that when said third field effect transistor is caused to conduct, the first and second output nodes are brought to approximately the same potential difference as exists between said first and second fixed sources of potential, without additional current flow through either one of said sixth and seventh field effect transistors.

Claim 27

An improved circuit as in claim 20 further comprising: a push pull amplifier having first and second input nodes, the first input node of said push pull amplifier being electrically coupled to the first output point, the second input node of said differential amplifier being electrically coupled to the second output point.

Claim 28

An improved circuit as in claim 20 further comprising: means for bringing said first and second input points to a potential level approximately equal to the potential level of said first fixed source of potential, said fourth and fifth field effect transistors bringing said first and second output points to a potential level approximately equal to the potential level of said first fixed source of potential, such that when either input point receives a potential level less than that of said first fixed source of potential, the corresponding one of said sixth and seventh field effect transistors conduct thereby conditioning one of said first and second field effect transistors to a lesser gate to source bias level than the other such that when said third field effect transistor is caused to conduct, the first and second output nodes are brought to approximately the same potential difference as exists between said first and second fixed sources of potential, without additional current flow through either one of said sixth and seventh field effect transistors.

Claim 29

An improved circuit as in claim 25 further comprising: an eighth field effect transistor having a drain, source and gate electrode and having its drain to source path connected between the first input node of said push pull amplifier and the first output point; a ninth field effect transistor having a drain, source and gate electrode, having its drain to source path coupled between the second input node of said differential amplifier and said second output point; and the gate electrodes of said eighth and ninth field effect transistors being coupled to each other and to a second pulsating source of potential.

Claim 30

An array of semiconductor memory cells as in claim 19 further comprising: an eighth field effect transistor having a drain, source and gate electrode and having its drain to source path connected between the first input node of said push pull amplifier and the first output point; a ninth field effect transistor having a drain, source and gate electrode, having its drain to source path coupled between the second input node of said differential amplifier and said second output point; and the gate electrodes of said eighth and ninth field effect transistors being coupled to each other and to a pulsating source of potential.

Claim 31

An array of semiconductor memory cells as in claim 17 further comprising: means connected between said plurality of bit lines and said sense amplifier latching circuit adapted to selectively connect one of a plurality of said pair of said bit lines to a selected one of said sense amplifier latching circuits.

Claim 32

In an electronic memory system, a sense amplifier latching circuit comprising: first and second sources of potential; first and second input nodes; first and second output nodes; first and second transistors, each having first and second controlled electrodes and a control electrode, said first controlled electrodes being electrically connected, said second controlled electrode of said first transistor being electrically connected to the control electrode of said second transistor, said second controlled electrode of said second transistor being electrically connected to the control electrode of said first transistor; said first output node being in electrical contact with said electrical connection between the second controlled electrode of said first transistor and the control electrode of said second transistor; said second output node being in electrical contact with said electrical connection between said second controlled electrode of said second transistor and the control electrode of said first transistor; a first impedance means electrically connected between said first source of potential and said first output node; a second impedance means electrically connected between said first source of potential and said second output node; a first isolation means electrically connected between said first input node and said first output node; a second isolation means electrically connected between said second input node and said second output node; and a third transistor having first and second controlled electrodes and a control electrode, the first controlled electrode of said third transistor being electrically connected to said second source of potential, the second controlled electrode of said third transistor being in electrical contact with said electrical connection between the first controlled electrodes of said first and second transistors, the control electrode of said third transistor being electrically connected to a third source of potential.

Claim 33

In an electronic memory system, a sense amplifier latching circuit comprising: first and second sources of potential; first and second input nodes; first and second output nodes; first and second transistors, each having first and second controlled electrodes and a control electrode, said first controlled electrodes being electrically connected, said second controlled electrode of said first transistor being electrically connected to the control electrode of said second transistor, said second controlled electrode of said second transistor being electrically connected to the control electrode of said first transistor; said first output node being in electrical contact with said electrical connection between the second controlled electrode of said first transistor and the control electrode of said second transistor; said second output node being in electrical contact with said electrical connection between said second controlled electrode of said second transistor and the control electrode of said first transistor; a first impedance means electrically connected between said first source of potential and said first output node; a second impedance means electrically connected between said first source of potential and said second output node; a first isolation means electrically connected between said first input node and said first output node; a second isolation means electrically connected between said second input node and said second output node; and a third transistor having first and second controlled electrodes and a control electrode, the first controlled electrode of said third transistor being electrically connected to said second source of potential, the second controlled electrode of said third transistor being in electrical contact with said electrical connection between the first controlled electrodes of said first and second transistors, the control electrode of said third transistor being electrically connected to a third source of potential.

Claim 34

A sense amplifier latching circuit as in claim 30 wherein said third source of potential is a variable source of potential.

Claim 35

A sense amplifier latching circuit as in claim 31 wherein said variable source of potential has two stable states.

Claim 36

A sense amplifier latching circuit as in claim 32 wherein said first and second sources of potential are fixed sources of potential.

Claim 37

A sense amplifier latching circuit as in claim 33 wherein a first one of the two stable states of said third source of potential approximates in value that of said first fixed source of potential while the second of the two stable states of said third source of potential approximates in value that of the second fixed source of potential.

Claim 38

A sense amplifier latching circuit as in claim 32 wherein the first stable state of said third source of potential biases said third transistor into its low impedance state, the second of said two stable states biasing said third transistor into its high impedance state.

Claim 39

A sense amplifier latching circuit as in claim 35 wherein a potential difference is applied to said first and second input nodes at a time when said third transistor is in its high impedance state.

Claim 40

A sense amplifier latching circuit as in claim 36 wherein said input signal causes one of said first and second isolation means to conduct thereby establishing a potential difference on the control electrodes of said first and second transistors such that when said third transistor is placed in its low impedance state, one of said first and second transistors conducts more current than the other until one of said first and second transistors is turned off and a potential difference between said first and second output nodes is established, said potential difference being approximately equal to the potential difference between said first and second fixed sources of potential.

Claim 41

A sense amplifier latching circuit as in claim 37 wherein said first and second input nodes are at a substantially equal potential level approximately equal to the value of the potential level of said first fixed source of potential prior to the application of an input signal.

Claim 42

A sense amplifier latching circuit as in claim 30 further comprising: a push pull amplifier having first and second input nodes, the first input node of said push pull amplifier being electrically coupled to the first output node, the second input node of said differential amplifier being electrically coupled to the second output node.

Claim 43

A sense amplifier latching circuit as in claim 30 wherein said first, second, and third transistors are field effect transistors.

Claim 44

A sense amplifier latching circuit as in claim 40 wherein said field effect transistors are enhancement mode field effect transistors.

Claim 45

A sense amplifier latching circuit as in claim 30 wherein said first and second impedance means comprise fourth and fifth field effect transistors, respectively, each having first and second controlled electrodes and a control electrode, said first controlled electrodes being electrically connected to said first source of potential, said second controlled electrode of said fourth field effect transistor being electrically connected to said first output node, said second controlled electrode of said fifth field effect transistor being electrically connected to said second output node.

Claim 46

A sense amplifier latching circuit as in claim 42 wherein said fourth and fifth field effect transistors are of the depletion mode type each having its control electrode electrically connected to its second controlled electrode, respectively.

Claim 47

A sense amplifier latching circuit as in claim 30 wherein said first and second isolation means comprise sixth and seventh field effect transistors each having first and second controlled electrodes and a control electrode.

Claim 48

A sense amplifier latching circuit as in claim 44 wherein said sixth and seventh field effect transistors are of the enhancement type each having an electrical connection between its second controlled electrode and its control electrode, respectively, said sixth field effect transistor having its first controlled electrode electrically connected to said first input node, said seventh field effect transistor having its first controlled electrode electrically connected to said second input node.

Claim 49

An array of semiconductor memory cells formed in a semiconductor substrate, said array comprising: a plurality of word lines arranged in parallel with each other each connected to a plurality of said cells arranged in a row; a plurality of bit lines, parallel to each other, arranged orthogonally to said word lines, a pair of said bit lines being operatively associated with each cell in a column of cells; a sense amplifier latching circuit as in claim 30 having its first input node electrically connected to a first one of said pair of said bit lines, said second input node connected to a second one of said pair of said bit lines.

Claim 50

An array of semiconductor memory cells as in claim 46 further comprising: means for bringing said first and second ones of said pair of bit lines to a potential level approximately equal to the potential of said first source of potential, said first and second isolation means being arranged to minimize current flow between said first and second bit lines and said first and second output nodes.

Claim 51

An array of semiconductor memory cells as in claim 47 further comprising: a push pull amplifier having first and second input nodes, the first input node of said push pull amplifier being electrically coupled to the first output node, the second input node of said differential amplifier being electrically coupled to the second input node.