Patent US4073005A successfully refreshed from Google Patents.
US4073005A
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US
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Multi-processor computer system
Assignee: Control Data Corp
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Filing: 1974-01-21
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Granted: 1978-02-07
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Expires: 1994-01-21
Abstract
Abstract Two or more processors share a large main memory in which are stored the programs and data sets on which the processors operate. Each processor operates independently from every other one, and selects its tasks for operation on the basis of information contained in tables which may be updated independently by each processor.
Inventors
- 👤 Thomas R. Parkin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:52
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F9/4881
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
528 words
Apparatus for processing a plurality of discrete computing tasks, each expressed as a sequence of digital computer instructions, at least one task including a call instruction requesting the performance of a task specified by the call instruction, and at least one task including a task suspension instruction, comprising: (A) an addressable main memory recording digit sequences contained in a record signal responsive thereto at the address specified by an address signal, and supplying in a data signal the digit sequence recorded at the address specified by the address signal responsive to a retrieve signal, and storing within predetermined areas a plurality of tasks and a task description table specifying the information necessary for activation and execution of each task; (B) a storage access unit having a plurality of associated pairs of input and output channels, and supplying record, retrieve and address signals to the main memory responsive to record and retrieve-specifying function codes accompanied by data and an address signal on any one of the plurality of input channels; and supplying retrieved data sequences on the output channel associated with the input channel receiving the function code specifying the retrieve function; and (C) a plurality of local processors whose elements can store and retrieve data in the main memory via a preselected input and output channel pair of the storage access unit, each processor comprising: (1) an addressable local memory accessible to all other elements of the local processor and including a current task cell; (2) task activation means receiving a call task signal identifying a task for forming responsive thereto an active table entry specifying the location of the identified task in main memory and containing a multi-state status flag indicating a ready state, and for issuing signals to the storage access unit causing the active table entry to be stored in an unused area of an active table in the main memory, each said area identified by an associated index; (3) task selection means for issuing signals to the storage access unit to cause at least one active table entry to be retrieved from the main memory responsive to an idle signal, for examining the status flag in each active table entry retrieved, and for, responsive to the ready state of the status flag in any retrieved active table entry, setting the current task cell to the index of the active table entry having such a status flag, and thereafter issuing signals to the storage access unit for (a) changing the status flag in the active table entry in the main memory indexed by the contents of the current task cell to an execute state and, next, (b) retrieving the task whose location is specified by the active table entry indexed by the contents of the current task cell and storing it in the local memory; and (4) task execution means for (a) executing each task indexed by the current task cell responsive to its storage in local memory, (b) supplying the idle signal to the task selection means responsive to detection of a task suspension instruction, and (c) supplying the call task signal to the task activation means responsive to detection of a call instruction.
Claim 2
Dependent Claim
528 words
Apparatus for processing a plurality of discrete computing tasks, each expressed as a sequence of digital computer instructions, at least one task including a call instruction requesting the performance of a task specified by the call instruction, and at least one task including a task suspension instruction, comprising: (A) an addressable main memory recording digit sequences contained in a record signal responsive thereto at the address specified by an address signal, and supplying in a data signal the digit sequence recorded at the address specified by the address signal responsive to a retrieve signal, and storing within predetermined areas a plurality of tasks and a task description table specifying the information necessary for activation and execution of each task; (B) a storage access unit having a plurality of associated pairs of input and output channels, and supplying record, retrieve and address signals to the main memory responsive to record and retrieve-specifying function codes accompanied by data and an address signal on any one of the plurality of input channels; and supplying retrieved data sequences on the output channel associated with the input channel receiving the function code specifying the retrieve function; and (C) a plurality of local processors whose elements can store and retrieve data in the main memory via a preselected input and output channel pair of the storage access unit, each processor comprising: (1) an addressable local memory accessible to all other elements of the local processor and including a current task cell; (2) task activation means receiving a call task signal identifying a task for forming responsive thereto an active table entry specifying the location of the identified task in main memory and containing a multi-state status flag indicating a ready state, and for issuing signals to the storage access unit causing the active table entry to be stored in an unused area of an active table in the main memory, each said area identified by an associated index; (3) task selection means for issuing signals to the storage access unit to cause at least one active table entry to be retrieved from the main memory responsive to an idle signal, for examining the status flag in each active table entry retrieved, and for, responsive to the ready state of the status flag in any retrieved active table entry, setting the current task cell to the index of the active table entry having such a status flag, and thereafter issuing signals to the storage access unit for (a) changing the status flag in the active table entry in the main memory indexed by the contents of the current task cell to an execute state and, next, (b) retrieving the task whose location is specified by the active table entry indexed by the contents of the current task cell and storing it in the local memory; and (4) task execution means for (a) executing each task indexed by the current task cell responsive to its storage in local memory, (b) supplying the idle signal to the task selection means responsive to detection of a task suspension instruction, and (c) supplying the call task signal to the task activation means responsive to detection of a call instruction.
Claim 3
Dependent Claim
352 words
The apparatus of claim 1 adapted for processing at least one task wherein the task suspension instruction comprises an end instruction in a predetermined sequence specifying the end of task execution, wherein the active table entry status flag for the task can assume delete and terminate states and each active table entry includes a called task field, wherein at least one task execution means further comprises means for supplying an end task signal responsive to detection of an end instruction; and wherein at least one task activation means further comprises means for including within the active table entry created responsive to each call task signal a calling task field containing the contents of the current task cell and means for supplying signals to the storage access unit causing the identity of the called task to be inserted in the called task field of the active table entry specified by the current task cell; and further comprising task termination means for, responsive to the end task signal: (i) supplying signals to the storage access unit causing the status flag in the active table entry indexed by the current task cell to be set to the terminate state; (ii) issuing a delete signal; (iii) responsive to each delete signal, examining the status flag of each active table entry indexed by the called task field of the active table entry indexed by the current task cell, and if the status flag of each such active table entry is in terminate state changing the status flag of the active table entry indexed by the current task cell to the delete state, and removing the index stored in the current task cell from the called task field of the active table entry specified by the calling task field; and (iv) examining the status flag in the active table entry indexed by the calling task field of the active table entry specified by the current task cell, and if in terminate state, inserting the calling task field of the active table entry indexed by the current task cell, in the current task cell, and issuing a delete signal.
Claim 4
Dependent Claim
202 words
The apparatus of claim 1 adapted for processing at least one task having in a predetermined sequence a set flag instruction including a digit sequence specifying a flag: wherein the main memory further comprises a storage area recording a flag table having an entry available for assigning to each flag and having a condition field having set and unset states and a waiting task field for recording at least one active table index; and wherein the task execution means in at least one pre-selected processor further comprises: (a) means for detecting a set flag instruction and responsive thereto, inspecting the flag table for an entry matching the specified flag, and for issuing a primary flag present signal upon detecting such match; and (b) flag setting means receiving the primary flag present signal and responsive thereto if the condition field of the flag table entry matching the flag specified by the set flag instruction is unset, issuing signals to the storage access unit causing this condition field to be changed to the set condition and the status flag in at least one active table entry indexed by the waiting task field of this flag table entry, to be set to its ready state.
Claim 5
Dependent Claim
52 words
The apparatus of claim 3 wherein one active table entry further comprises a starting address field recording a local memory address; and wherein at least one of the task execution means further comprises means for causing execution of the loaded task to commence at the address recorded in the starting address field.
Claim 6
Dependent Claim
73 words
The apparatus of claim 3, wherein the set flag instruction detecting means further comprises means for issuing a primary flag absent signal responsive to failure to detect a match of the specified flag during flag table inspection, and flag inserting means receiving the primary flag absent signal for, responsive thereto, establishing a flag table entry matching the flag specified by the set flag instruction and having its condition field in the set state.
Claim 7
Dependent Claim
425 words
The apparatus of claim 3 adapted for processing at least one task having in a predetermined sequence a test flag instruction including a digit sequence specifying a flag: wherein each active table entry assigned to a task containing a test flag instruction has a status flag capable of assuming a wait state, a temporary storage address field for recording a main memory address, and a starting address field for recording a local memory address; wherein the task execution means in each preselected processor further comprises means for detecting a test flag instruction and responsive thereto supplying a test flag signal, means for halting execution of instructions and issuing an idle signal responsive to a flag unset signal, and means for starting execution of each retrieved task at the address specified in the starting address field of the active table entry indexed by the contents of the current task cell; and wherein each preselected processor further comprises: (A) flag table lookup means for issuing a secondary flag present signal responsive to a flag table entry matching the flag specified by the test flag instruction, and a secondary flag absent signal otherwise; (B) flag testing means receiving the secondary flag present and absent signals for, responsive to the secondary flag absent signal, issuing signals to the storage access unit establishing a flag table entry in the flag table assigned to the flag specified by the test flag instruction and having its condition flag in the unset state and its waiting task field containing the contents of the current task cell, and issuing a flag unset signal to the task execution means of the processor involved; and responsive to the secondary flag present signal, testing the condition flag in the flag table entry specified by the test flag instruction and if unset, (i) issuing a flag unset signal to the task execution means of the processor involved, and (ii) issuing signals to the storage access unit (a) causing the area of the local memory holding the current task to be recorded in a temporary task storage area of main memory and (b) within the active table entry indexed by the current task cell, causing the address of the temporary task storage area in main memory to be recorded in the temporary storage address field, the status flag to be changed to its wait state and the address of the instruction following the test flag instruction to be recorded in the starting address field, and lastly, issuing an idle signal to the task selection means of the processor involved.
Claim 8
Dependent Claim
75 words
The apparatus of claim 1 wherein the task activation means further comprises means for including in each active table entry a digit sequence specifying at least one processor which can execute the task, and wherein the task selection means further comprises means for determining whether the processor of which it forms a part is, according to the active table entry, specified as able to execute the task, and if not excluding the task from selection.
Claim 9
Dependent Claim
75 words
The apparatus of claim 1 further comprising an interlock flip-flop having set and cleared states and wherein each task execution means further comprises means responsive to suspension of task execution for examining the interlock flip-flop and if set, waiting until it is cleared, and if cleared, setting it, and issuing the idle signal, and wherein the task selection means further comprises means for clearing the interlock flip-flop after setting a status flag to execute state.
Claim 10
Dependent Claim
22 words
The apparatus of claim 8 including means for allowing only one task execution means at a time to examine the interlock flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-06 | 1981-08-08 | 1982-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-06 | 1985-08-08 | 1986-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-06 | 1989-08-08 | 1990-02-07 | $7700.00 | Window Closed / Lapsed |