Multi-mode data processing system

Claim 2

In a data processor Having logic means for accomplishing binary logic operations on data, instruction issuing means for issuing process instructions for manipulating data, and accumulator means for accomplishing arithmetic operations on data, the improvement comprising: register means for storing data, said register means comprising a plurality of individually addressable portions; merge network means connected to said register means and to said logic means and said accumulator means for selectively writing data into addressed portions of said register means from said logic means and said accumulator means; distribution network means connected to said register means and to said logic means and said accumulator means for selectively reading data out of addressed portions of said register means to said logic means and said accumulator means; and control means connected to said instruction issuing means and to said merge network means and said distribution network means and responsive to said process instructions for selectively operating said merge network means to write data into selected register portions from selected logic means and accumulator means, and for selectively operating said distribution network means to read data from selected register portions to selected logic means and accumulator means.

Claim 3

Apparatus according to claim 1 wherein said logic means includes means for accomplishing shift, long addition, Boolean logic, masking, floating point pack and floating point un-pack operations, said apparatus further including first and second operand register means connected between said logic means and said distribution network means, said control means being operable to selectively operate said distribution network means to read data from selected register portions to selected ones of said operand register means.

Claim 4

Apparatus according to claim 1 wherein said merge network means and said distribution network means are connected to a memory means, said control means being operable in response to said process instructions to selectively operate said merge network means to write data into selected register portions from said memory means and to selectively operate said distribution network to read data from selected register portions into said memory means.

Claim 5

Apparatus according to claim 3 wherein said logic means includes means for accomplishing shift, long addition, Boolean logic, masking, floating point pack and floating point un-pack operations, said apparatus further including first and second operand register means connected between said logic means and said distribution network means, said control means being operable to selectively operate said distribution network means to read data from selected register portions to selected ones of said operand register means.

Claim 6

Apparatus according to claim 3 wherein said control means includes instruction word storage means and instruction address storage means, said instruction word storage means being adapted to receive process instructions from said memory, said instruction address storage means being connected to said register means to receive instruction addresses from selected portions of said register means, said instruction address storage means being operable in response to an instruction address to cause an output of a corresponding process instruction from said instruction word storage means, and translator means responsive to an instruction word from said instruction word storage means for selectively operating said distribution network means and said merge network means.

Claim 7

Apparatus according to claim 5 wherein said logic means includes means for accomplishing shift, long addition, Boolean logic, masking, floating point pack and floating point un-pack operations, said apparatus further including first and second operand register means connected between said logic means and said distribution network means, said control means being operable to selectively operate said distribution network means to rEad data from selected register portions to selected ones of said operand register means.

Claim 8

Apparatus according to claim 6 further including means for transferring at least a portion of said instruction addresses to a selected one of said operand register means.

Claim 9

Apparatus according to claim 7 further including means for transferring at least a portion of said process instructions to a selected one of said operand registers.

Claim 10

Apparatus according to claim 6 further including means for transferring at least a portion of said process instructions to a selected one of said operand registers.

Claim 11

Apparatus according to claim 3 further including instruction word register means adapted to receive instruction words from said memory means for controlling data processing operations, memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program; reference address register means providing a reference address unique to said object program; second control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address; and gate means for selectively operating said second control means.

Claim 12

Apparatus according to claim 10 wherein each program address is unique to an individual instruction of said object program and is referenced from said reference address, first increment means for incrementally altering said program address to provide successive, incremental program addresses, whereby upon operation of said gate means, said second control means operates to form said predetermined access addresses by combining said reference address and at least a portion of each successive program address.

Claim 13

Apparatus according to claim 11 further including exchange address register means providing a resident program address representative of an address of a program stored in said memory means outside of the field length of said object program, second increment means for incrementally increasing said resident program address to supply successive, incremental resident program addresses, said gate means being operable to condition said second control means to pass said successive resident program addresses to said memory access control means.

Claim 14

Apparatus according to claim 12 wherein said second control means includes adder means having first and second inputs for binarily adding binary signals appearing at said first and second inputs, means for applying said incremental program addresses to the first input of said adder means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, means for applying said reference address to the first input of said AND gate means, and select means for selectively applying an enable signal to the second input of said AND gate means.

Claim 15

Apparatus according to claim 13 wherein said select means includes issue means associated with said instruction word register means for issuing said enable signal upon issuance of an individual instruction of said object program.

Claim 16

Apparatus according to claim 13 wherein said select means includes exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said second control means being responsive to said reference address and said exchange address to add said reference address to at least a portion of said Exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word register means.

Claim 17

Apparatus according to claim 15 wherein said select means further includes issue means associated with said instruction word register means for issuing an enable signal upon issuance of an individual instruction of said object program, and OR gate means connected to said issue means and to said exchange means for applying the enable signals from said issue means and from said exchange means to the second input of said AND gate means.

Claim 18

Apparatus according to claim 10 wherein said second control means includes adder means having first and second inputs for binarily adding binary signals appearing at said first and second inputs, means for applying said program addresses to the first input of said adder means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, means for applying said reference address to the first input of said AND gate means, and select means for selectively applying an enable signal to the second input of said AND gate means.

Claim 19

Apparatus according to claim 17 wherein said select means includes issue means associated with said instruction word register means for issuing said enable signal upon issuance of an individual instruction of said object program.

Claim 20

Apparatus according to claim 17 wherein said select means includes exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said second control means being responsive to said reference address and said exchange address to add said reference address to at least a portion of said exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word register means.

Claim 21

Apparatus according to claim 19 wherein said select means further includes issue means associated with said instruction word register means for issuing an enable signal upon issuance of an individual instruction of said object program, and OR gate means connected to said issue means and to said exchange means for applying the enable signals from said issue means and from said exchange means to the second input of said AND gate means.

Claim 22

Apparatus according to claim 10 wherein said processor further includes address stack means connected to said program address register means and containing one or more program addresses associated with instruction words stored in said instruction word register means, and means for applying data from said register means to said program address register means, said improvement further including out-of-stack means responsive to a non-coincidence between the data in said program address register means and the addresses in said address stack means for providing an enable signal, first select means responsive to said enable signal from said out-of-stack means for accepting data from said program address register means, said last-named data comprising first and second pluralities of bits, said second control means including first adder means connected to said first select means for receiving said first plurality of bits, said first adder means being operable in response to operation of said gate means to binarily add said reference address to said first plurality of bits, said access control means being connected to said first select means and to said first adder means to receive the output from said adder means and said second plurality of bits.

Claim 23

Apparatus according to claim 21 further including instruction feTch address means operable to receive data from said program address register means to forward said data to said first select means, and increment means for incrementally altering data in said instruction fetch address means to provide successive, incremental data.

Claim 24

Apparatus according to claim 22 further including exchange means providing an exchange address representative of the relative location in said memory means of an exchange routine outside of the field length of said object program, said exchange address being relative to said reference address, second select means responsive to said out-of-stack means for transferring said exchange address from said exchange means to said instruction fetch address means, incremental counter means associated with said exchange means for counting the number of transfers of data from said exchange means to said instruction fetch address means, and second adder means for adding the count in said counter means to data in said instruction fetch address means.

Claim 25

Apparatus according to claim 23 wherein said gate means includes an AND gate means having a first input connected to said reference address register means and a second input connected to receive an enable signal, said exchange means providing an enable signal for said AND gate.

Claim 26

Apparatus according to claim 24 wherein said gate means further includes OR gate means having a first input connected to receive an enable signal from said exchange means and having an output connected to the second input of said AND gate means, issue control means associated with said instruction word register means for issuing enable signals upon issuance of instructions of said object program, and means connecting the second input of said OR gate means to receive enable signals from said issue control means.

Claim 27

In a data processor having an instruction word register means adapted to receive instruction words from a memory means for controlling data processing operations and having memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, the improvement comprising address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program; reference address register means providing a reference address unique to said object program, each of said program addresses being referenced from said reference address; control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address; gate means for selectively operating said control means; first increment means for incrementally altering said program address to provide successive, incremental program addresses, whereby upon operation of said gate means, said control means operates to form said predetermined access addresses by combining said reference address and at least a portion of each successive program address; exchange address register means providing a resident program address representative of an address of a program stored in said memory means outside of the field length of said object program; and second increment means for incrementally increasing said resident program address to supply successive, incremental resident program addresses, said gate means being operable to condition said control means to pass said successive resident program addresses to said memory access control means.

Claim 28

In a data processor having an instruction word register means adapted to receive instruction words from a memory means for controlling data processing operations and having memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, the improvement comprising address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program; reference address register means providing a reference address unique to said object program, each of said program addresses being referenced from said reference address; control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address; gate means for selectively operating said control means; first increment means for incrementally altering said program address to provide successive, incremental program addresses, whereby upon operation of said gate means, said control means operates to form said predetermined access addresses by combining said reference address and at least a portion of each successive program address; exchange address register means providing a resident program address representative of an address of a program stored in said memory means outside of the field length of said object program; and second increment means for incrementally increasing said resident program address to supply successive, incremental resident program addresses, said gate means being operable to condition said control means to pass said successive resident program addresses to said memory access control means.

Claim 29

Apparatus according to claim 26 wherein said control means includes adder means having first and second inputs for binarily adding binary signals appearing at said first and second inputs, means for applying said incremental program addresses to the first input of said adder means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, means for applying said reference address to the first input of said AND gate means, and select means for selectively applying an enable signal to the second input of said AND gate means.

Claim 30

Apparatus according to claim 27 wherein said select means includes issue means associated with said instruction word register means for issuing said enable signal upon issuance of an individual instruction of said object program.

Claim 31

Apparatus according to claim 27 wherein said select means includes exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said control means being responsive to said reference address and said exchange address to add said reference address to at least a portion of said exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word register means.

Claim 32

Apparatus according to claim 29 wherein said select means further includes issue means associated with said instruction word register means for issuing an enable signal upon issuance of an individual instruction of said object program, and OR gate means connected to said issue means and to said exchange means for applying the enable signals from said issue means and from said exchange means to the second input of said AND gate means.

Claim 33

In a data processor having an instruction word register means adapted to receive instruction words from a memory means for controlling data processing operations and having memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, the improvement comprising address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program; reference address register means providing a reference address unique to said object program; control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, said control means including adder means having first and second inputs for binarily adding binary signals at said first and second inputs, and means for applying said program addresses to the first input of said adder means; gate means for selectively operating said control means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, and means for applying said reference address to the first input of said AND gate means; and select means for selectively applying an enable signal to the second input of said AND gate means, said select means including exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said control means being responsive to said reference address and to said exchange address to add said reference address to at least a portion of said exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word register means.

Claim 34

In a data processor having an instruction word register means adapted to receive instruction words from a memory means for controlling data processing operations and having memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, the improvement comprising address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program; reference address register means providing a reference address unique to said object program; control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, said control means including adder means having first and second inputs for binarily adding binary signals at said first and second inputs, and means for applying said program addresses to the first input of said adder means; gate means for selectively operating said control means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, and means for applying said reference address to the first input of said AND gate means; and select means for selectively applying an enable signal to the second input of said AND gate means, said select means including exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said control means being responsive to said reference address and to said exchange address to add said reference address to at least a portion of said exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word register means.

Claim 35

Apparatus according to claim 31 whereiN said select means further includes issue means associated with said instruction word register means for issuing an enable signal upon issuance of an individual instruction of said object program, and OR gate means connected to said issue means and to said exchange means for applying the enable signals from said issue means and from said exchange means to the second input of said AND gate means.

Claim 36

In a data processor having an instruction word register means adapted to receive instruction words from a memory means for controlling data processing operations, memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, the improvement comprising address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program; address stack means connected to said program address register means and containing one or more program addresses associated with instruction words stored in said instruction word register means, X register means in said processor for storing data, and means for applying data from said X register means to said program address register means, reference address register means providing a reference address unique to said object program; out-of-stack means responsive to a non-coincidence between the data in said program address register means and the addresses in said address stack means for providing an enable signal; first select means responsive to said enable signal from said out-of-stack means for accepting data from said program address register means, said last-named data comprising first and second pluralities of bits; control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, said control means including first adder means connected to said first select means for receiving said first plurality of bits, said access control means being connected to said first select means and said first adder means to receive the output from said adder means and said second plurality of bits; and gate means for selectively operating said control means, said first adder means being operable in response to operation of said gate means to binarily add said reference address to said first plurality of bits.

Claim 37

In a data processor having an instruction word register means adapted to receive instruction words from a memory means for controlling data processing operations, memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, the improvement comprising address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program; address stack means connected to said program address register means and containing one or more program addresses associated with instruction words stored in said instruction word register means, X register means in said processor for storing data, and means for applying data from said X register means to said program address register means, reference address register means providing a reference address unique to said object program; out-of-stack means responsive to a non-coincidence between the data in said program address register means and the addresses in said address stack means for providing an enable signal; first select means responsive to said enable signal from said out-of-stack means for accepting data from said program address register means, said last-named data comprising first and second pluralities of bits; control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, said control means including first adder means connected to said first select means for receiving said first plurality of bits, said access control means being connected to said first select means and said first adder means to receive the output from said adder means and said second plurality of bits; and gate means for selectively operating said control means, said first adder means being operable in response to operation of said gate means to binarily add said reference address to said first plurality of bits.

Claim 38

Apparatus according to claim 33, further including instruction fetch address means operable to receive data from said program address register means to forward said data to said first select means, and increment means for incrementally altering data in said instruction fetch address means to provide successive, incremental data.

Claim 39

Apparatus according to claim 34 further including exchange means providing an exchange address representative of the relative location in said memory means of an exchange routine outside of the field length of said object program, said exchange address being relative to said reference address, second select means responsive to said out-of-stack means for transferring said exchange address from said exchange means to said instruction fetch address means, incremental counter means associated with said exchange means for counting the number of transfers of data from said exchange means to said instruction fetch address means, and second adder means for adding the count in said counter means to data in said instruction fetch address means.

Claim 40

Apparatus according to claim 35 wherein said gate means includes an AND gate means having a first input connected to said reference address register means and a second input connected to receive an enable signal, said exchange means providing an enable signal for said AND gate.

Claim 41

Apparatus according to claim 36 wherein Said gate means further includes OR gate means having a first input connected to receive an enable signal from said exchange means and having an output connected to the second input of said AND gate means, issue control means associated with said instruction word register means for issuing enable signals upon issuance of instructions of said object program, and means connecting the second input of said OR gate means to receive enable signals from said issue control means.

Claim 42

In a multiprocessor computer system having: a. a plurality of individual data processors, each of said processors having: i. logic means for accomplishing binary logic operations on data, ii. instruction issuing means for issuing process instructions for manipulating data, iii. accumulator means for accomplishing arithmetic operations on data, iv. register means for storing data, said register means comprising a plurality of individually addressable register portions, v. merge network means connected to said register means and to said logic means and to said accumulator means for selectively writing data into addressed portions of said register means from said logic means and said accumulator means, vi. distribution network means connected to said register means and to said logic means and to said accumulator means for selectively reading data out of addressed portions of said register means to said logic means and said accumulator means, and vii. first control means connected to said instruction issuing means and to said merge network means and to said distribution network means and responsive to said process instructions for selectively operating said merge network means to write data into selected register portions from selected logic means and selected accumulator means, and for selectively operating said distribution network to read data from selected register portions to selected logic means and selected accumulator means; b. memory means common to each of said data processors and connected to ech of said first control means; c. input/output means operatively associated with said memory means; the improvement comprising: d. interlock register means having an output connected to each of said merge network means and having an input connected to each of said distribution network means; and e. second control means associated with each of said data processors and connected to said interlock register means, said second control means being operable in response to process instructions to selectively read binary coded information from selected register portions of the respective register means to said interlock register means and being further operable in response to process instructions to selectively write binary coded information into selected register portions of the respective register means from said interlock register means.

Claim 43

In a multiprocessor computer system having: a. a plurality of individual data processors, each of said processors having: i. logic means for accomplishing binary logic operations on data, ii. instruction issuing means for issuing process instructions for manipulating data, iii. accumulator means for accomplishing arithmetic operations on data, iv. register means for storing data, said register means comprising a plurality of individually addressable register portions, v. merge network means connected to said register means and to said logic means and to said accumulator means for selectively writing data into addressed portions of said register means from said logic means and said accumulator means, vi. distribution network means connected to said register means and to said logic means and to said accumulator means for selectively reading data out of addressed portions of said register means to said logic means and said accumulator means, and vii. first control means connected to said instruction issuing means and to said merge network means and to said distribution network means and responsive to said process instructions for selectively operating said merge network means to write data into selected register portions from selected logic means and selected accumulator means, and for selectively operating said distribution network to read data from selected register portions to selected logic means and selected accumulator means; b. memory means common to each of said data processors and connected to ech of said first control means; c. input/output means operatively associated with said memory means; the improvement comprising: d. interlock register means having an output connected to each of said merge network means and having an input connected to each of said distribution network means; and e. second control means associated with each of said data processors and connected to said interlock register means, said second control means being operable in response to process instructions to selectively read binary coded information from selected register portions of the respective register means to said interlock register means and being further operable in response to process instructions to selectively write binary coded information into selected register portions of the respective register means from said interlock register means.

Claim 44

Apparatus according to claim 38 wherein said merge network means and said distribution network means are connected to said memory means, said first control means being operable in response to said process instruction to selectively operate said merge network means to write data into selected register portions from said memory means and to selectively operate said distribution network to read data from selected register portions into said memory means.

Claim 45

Apparatus according to claim 39 wherein said first control means includes instruction word storage means and instruction address storage means, said instruction word storage means being adapted to receive process instructions from said memory, said instruction address storage means being connected to said register means to receive instruction addresses from selected portions of said register means, said instruction address storage means being operable in response to an instruction address to cause an output of a corresponding process instruction from said instruction word storage means, and translator means responsive to an instrucTion word from said instruction word storage means for selectively operating said distribution network means and said merge network means.

Claim 46

Apparatus according to claim 40 wherein said logic means includes means for accomplishing shift, long addition, Boolean logic, masking, floating point pack and floating point un-pack operations, said apparatus further including first and second operand register means connected between said logic means and said distribution network means, said first control means being operable to selectively operate said distribution network means to read data from selected register portions to selected ones of said operand register means.

Claim 47

Apparatus according to claim 40 further including means for transferring at least a portion of said instruction addresses to a selected one of said operand register means.

Claim 48

Apparatus according to claim 42 further including means for transferring at least a portion of said process instructions to a selected one of said operand registers.

Claim 49

Apparatus according to claim 40 further including means for transferring at least a portion of said process instructions to a selected one of said operand registers.

Claim 50

Apparatus according to claim 40 wherein said first named control means is connected to said translator means and responsive to the output therefrom.

Claim 51

Apparatus according to claim 40 wherein each processor further includes memory access control means for conditioning said memory means to transmit process instructions to said instruction word storage means in accordance with predetermined access addresses, address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program, reference address register means providing a reference address unique to said object program, third control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address; and gate means for selectively operating said third control means.

Claim 52

Apparatus according to claim 46 wherein each program address is unique to individual instruction of said object program and is referenced from said reference address, first increment means for incrementally altering said program address to provide successive, incremental program addresses, whereby upon operation of said gate means, said third control means operates to form said predetermined access addresses by combining said reference address and at least a portion of each successive program address.

Claim 53

Apparatus according to claim 47 further including exchange address register means providing a resident program address representative of an address of a program stored in said memory means outside of the field length of said object program, second increment means for incrementally increasing said resident program address to supply successive, incremental resident program addresses, said gate means being operable to condition said third control means to pass said successive resident program addresses to said memory access control means.

Claim 54

Apparatus according to claim 48 wherein said third control means includes adder means having first and second inputs for binarily adding binary signals appearing at said first and second inputs, means for applying said incremental program addresses to the first input of said adder means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, means for applying said reference address to the first input of said AND gate means, and select means for selectively applying an enable signal to the second input of said AND gate means.

Claim 55

Apparatus according to claim 49 wherein said select means includes said translator means for issuing said enable signal upon issuance of an individual instruction of said object program from said instruction word storage means.

Claim 56

Apparatus according to claim 49 wherein said select means includes exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said third control means being responsive to said reference address and said exchange address to add said reference address to at least a portion of said exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word storage means.

Claim 57

Apparatus according to claim 51 wherein said select means further includes said translator means for issuing an enable signal upon issuance of an individual instruction of said object program from said instruction word storage means, and OR gate means connected to said issue means and to said exchange means for applying the enable signals from said issue means and from said exchange means to the second input of said AND gate means.

Claim 58

Apparatus according to claim 46, wherein said third control means includes adder means having first and second inputs for binarily adding binary signals appearing at said first and second inputs, means for applying said program addresses to the first input of said adder means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, means for applying said reference address to the first input of said AND gate means, and select means for selectively applying an enable signal to the second input of said AND gate means.

Claim 59

Apparatus according to claim 53 wherein said select means includes issue means associated with said instruction word register means for issuing said enable signal upon issuance of an individual instruction of said object program.

Claim 60

Apparatus according to claim 53 wherein said select means includes exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said third control means being responsive to said reference address and said exchange address to add said reference address to at least a portion of said exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word register means.

Claim 61

Apparatus according to claim 55 wherein said select means further includes issue means associated with said instruction word register means for issuing an enable signal upon issuance of an individual instruction of said object program, and OR gate means connected to said issue means and to said exchange means for applying the enable signals from said issue means and from said exchange means for applying the enable signals from said issue means and from said exchange means to the second input of said AND gate means.

Claim 62

Apparatus according to claim 46 wherein each of said data processors further include address stack means connected to said program address register means and containing one or more program addresses associated with instruction words stored in said instruction word register means, and means for applying data from said register means to said program address register means, out-of-stack means responsive to a non-coincidence between the data in said program address register means and the addresses in said address stack means for providing an enable signal, first select means responsive to said enable signal from said out-of-stacK means for accepting data from said program address register means, said last-named data comprising first and second pluralities of bits, said third control means including first adder means connected to said first select means for receiving said first plurality of bits, said first adder means being operable in response to operation of said gate means to binarily add said reference address to said first plurality of bits, said access control means being connected to said first adder means to receive the output from said adder means and said second plurality of bits.

Claim 63

Apparatus according to claim 57 further including instruction fetch address means operable to receive data from said program address register means to forward said data to said first select means, and increment means for incrementally altering data in said instruction fetch address means to provide successive, incremental data.

Claim 64

Apparatus according to claim 58 further including exchange means providing an exchange address representative of the relative location in said memory means of an exchange routine outside of the field length of said object program, said exchange address being relative to said reference address, second select means responsive to said out-of-stack means for transferring said exchange address from said exchange means to said instruction fetch address means, incremental counter means associated with said exchange means for counting the number of transfers of data from said exchange to said instruction fetch address means, and second adder means for adding the count in said counter means to data in said instruction fetch address means.

Claim 65

Apparatus according to claim 59 wherein said gate means includes an AND gate means having a first input connected to said reference address register means and a second input connected to receive an enable signal, said exchange means providing an enable signal for said AND gate.

Claim 66

Apparatus according to claim 60 wherein said gate means further includes OR gate means having a first input connected to receive an enable signal from said exchange means and having an output connected to the second input of said AND gate means, issue control means associated with said instruction word register means for issuing enable signals upon issuance of instructions of said object program, and means connecting the second input of said OR gate means to receive enable signals from said issue control means.

Claim 67

In a multiprocessor computer system having: a. memory means; b. a plurality of individual data processors connected to said memory means, said data processors having: i. register means for storing data, said register means comprising a plurality of individually addressable register portions, ii. logic means connected to said register means for performing arithmetic, addressing and indexing functions, iii. instruction word register means adapted to receive instruction words from said memory means, iv. first control means responsive to instruction words from said instruction word register means for selectively operating said register portions to selectively read binary coded information from selected register portions to said logic means, and to selectively write binary coded information into selected register portions from said logic means, v. memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, and vi. address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program, reference address register means providing a reference address unique to said object program, each program address being unique to an individual instruction of said object program and referenCed from said reference address, second control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, exchange address register means providing a resident program address representative of an address of a program stored in said memory means outside of the field length of said object program, first increment means for incrementally altering said program address to provide successive, incremental program addresses, second increment means for incrementally increasing said resident program address to supply successive, incremental resident program addresses, and gate means for selectively conditioning said second control means to form said predetermined access addresses by combining said reference address and at least a portion of each successive program address and to pass said successive resident program address to said memory access control means, and c. input/output means operatively associated with said memory means; the improvement comprising: d. interlock register means having an output connected to an input of each of said first-named register means and having an input connected to an output of each of said first-named register means; and e. third control means associated with each of said data processors and connected to said interlock register means, said third control means being operable in response to process instructions from said first control means to selectively read binary coded information from selected register portions of the respective first-named register means to said interlock register means and being further operable in response to process instructions from said first control means to selectively write binary coded information into selected register portions of the respective first-named register means from said interlock register means.

Claim 68

In a multiprocessor computer system having: a. memory means; b. a plurality of individual data processors connected to said memory means, said data processors having: i. register means for storing data, said register means comprising a plurality of individually addressable register portions, ii. logic means connected to said register means for performing arithmetic, addressing and indexing functions, iii. instruction word register means adapted to receive instruction words from said memory means, iv. first control means responsive to instruction words from said instruction word register means for selectively operating said register portions to selectively read binary coded information from selected register portions to said logic means, and to selectively write binary coded information into selected register portions from said logic means, v. memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, and vi. address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing a program address indicative of individual data processing instructions of an object program, reference address register means providing a reference address unique to said object program, each program address being unique to an individual instruction of said object program and referenCed from said reference address, second control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, exchange address register means providing a resident program address representative of an address of a program stored in said memory means outside of the field length of said object program, first increment means for incrementally altering said program address to provide successive, incremental program addresses, second increment means for incrementally increasing said resident program address to supply successive, incremental resident program addresses, and gate means for selectively conditioning said second control means to form said predetermined access addresses by combining said reference address and at least a portion of each successive program address and to pass said successive resident program address to said memory access control means, and c. input/output means operatively associated with said memory means; the improvement comprising: d. interlock register means having an output connected to an input of each of said first-named register means and having an input connected to an output of each of said first-named register means; and e. third control means associated with each of said data processors and connected to said interlock register means, said third control means being operable in response to process instructions from said first control means to selectively read binary coded information from selected register portions of the respective first-named register means to said interlock register means and being further operable in response to process instructions from said first control means to selectively write binary coded information into selected register portions of the respective first-named register means from said interlock register means.

Claim 69

Apparatus according to claim 62 wherein said second control means includes adder means having first and second inputs for binarily adding binary signals appearing at said first and second inputs, means for applying said incremental program addresses to the first input of said adder means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, means for applying said reference address to the first input of said AND gate means, and select means for selectively applying an enable signal to the second input of said AND gate means.

Claim 70

Apparatus according to claim 63 wherein said select means includes issue means associated with said instruction word register means for issuing said enable signal upon issuance of an individual instruction of said object program.

Claim 71

Apparatus according to claim 63 wherein said select means includes exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said second control means being responsive to said reference address and said exchange address to add said reference address to at least a portion of said exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word register means.

Claim 72

Apparatus according to claim 65 wherein said select means further includes issue means associated with said instruction word register means for issuing an enable signal upon issuance of an individual instruction of said object program, and OR gate means connected to said issue means and to said exchange means for applying the enable signals from said issue means and from said exchange means to the second input of said AND gate means.

Claim 73

In a multiprocessor system having: a. memory meAns; b. a plurality of individual data processors connected to said memory means, said data processors having: i. register means for storing data, said register means comprising a plurality of individually addressable register portions, ii. logic means connected to said register means for performing arithmetic, addressing and indexing functions, iii. instruction word register means adapted to receive instruction words from said memory means, iv. first control means responsive to instruction words from said instruction word register means for selectively operating said register portions to selectively read binary coded information from selected register portions to said logic means, and to selectively write binary coded information into selected register portions from said logic means, v. memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, vi. address means connected to said memory access control means for generating said predetermined access addresses, said address means including: program address register means providing a program address indicative of individual data processing instructions of an object program, reference address register means providing a reference address unique to said object program, second control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, said second control means including adder means having first and second inputs for binarily adding binary signals appearing at said first and second inputs, and means for applying said program addresses to the first input of said adder means, and gate means for selectively operating said second control means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, means for applying said reference address to the first input of said AND gate means, and vii. select means for selectively applying an enable signal to the second input of said AND gate means, said select means including exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said second control means being responsive to said reference address and said exchange address to add said reference address to at least a portion of said exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word register means; and c. input/output means operatively associated with said memory means; the improvement comprising: d. interlock register means having an output connected to an input of each of said first-named register means and having an input connected to an output of each of said first-named register means; and e. third control means associated with each of said data processors and connected to said interlock register means, said third control means being operable in response to process instructions from said first control means to selectively read binary coded information from selected register portions of the respective first-named register means to said interlock register means and being further operable in response to process instructions from said first control means to selectively write binary coded information into selected register portions of the respective first-named register means from said interlock register.

Claim 74

In a multiprocessor system having: a. memory meAns; b. a plurality of individual data processors connected to said memory means, said data processors having: i. register means for storing data, said register means comprising a plurality of individually addressable register portions, ii. logic means connected to said register means for performing arithmetic, addressing and indexing functions, iii. instruction word register means adapted to receive instruction words from said memory means, iv. first control means responsive to instruction words from said instruction word register means for selectively operating said register portions to selectively read binary coded information from selected register portions to said logic means, and to selectively write binary coded information into selected register portions from said logic means, v. memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, vi. address means connected to said memory access control means for generating said predetermined access addresses, said address means including: program address register means providing a program address indicative of individual data processing instructions of an object program, reference address register means providing a reference address unique to said object program, second control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, said second control means including adder means having first and second inputs for binarily adding binary signals appearing at said first and second inputs, and means for applying said program addresses to the first input of said adder means, and gate means for selectively operating said second control means, said gate means including AND gate means having first and second inputs and an output, means connecting the output of said AND gate means to the second input of said adder means, means for applying said reference address to the first input of said AND gate means, and vii. select means for selectively applying an enable signal to the second input of said AND gate means, said select means including exchange means providing an exchange address representative of the relative location in said memory means of an exchange program routine outside of the field length of said object program, said exchange address being relative to said reference address, said second control means being responsive to said reference address and said exchange address to add said reference address to at least a portion of said exchange address upon operation of said AND gate means, said exchange means providing said enable signal to said AND gate means upon issuance of an exchange program by said instruction word register means; and c. input/output means operatively associated with said memory means; the improvement comprising: d. interlock register means having an output connected to an input of each of said first-named register means and having an input connected to an output of each of said first-named register means; and e. third control means associated with each of said data processors and connected to said interlock register means, said third control means being operable in response to process instructions from said first control means to selectively read binary coded information from selected register portions of the respective first-named register means to said interlock register means and being further operable in response to process instructions from said first control means to selectively write binary coded information into selected register portions of the respective first-named register means from said interlock register.

Claim 75

Apparatus according to claim 67 wherein said select means further includes issue means associated with said instruction word register means for issuing an enable signal upon iSsuance of an individual instruction of said object program, and OR gate means connected to said issue means and to said exchange means for applying the enable signals from said issue means and from said exchange means to the second input of said AND gate means.

Claim 76

In a multiprocessor computer system having: a. memory means; b. a plurality of individual data processors connected to said memory means, said data processors having: i. X register means for storing data, said register means comprising a plurality of individually addressable register portions, ii. logic means connected to said register means for performing arithmetic, addressing and indexing functions, iii. instruction word register means adapted to receive instruction words from said memory means, iv. first control means responsive to instruction words from said instruction word register means for selectively operating said register portions to selectively read binary coded information from selected register portions to said logic means, and to selectively write binary coded information into selected register portions from said logic means, v. memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, vi. address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing program address indicative of individual data processing instructions of an object program, reference address register means providing a reference address unique to said object program, second control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, and gate means for selectively operating said second control means; vii. address stack means connected to said program address register means and containing one or more program addresses associated with instruction words stored in said instruction word register means, and means for applying data from said X register means to said program address register means; viii. out-of-stack means responsive to a non-coincidence between the data in said program address register means and the addresses in said address stack means for providing an enable signal; and ix. first select means responsive to said enable signal from said out-of-stack means for accepting data from said program address register means, said last-named data comprising first and second plurality of bits, said second control means including first adder means connected to said first select means for receiving said first plurality of bits, said first adder means being operable in response to operation of said gate means to binarily add said reference address to said first plurality of bits, said access control means being connected to said first adder means to receive the output from said adder means to receive the output from said adder means and said second plurality of bits; and c. input/output means operatively associated with said memory means; the improvement comprising: d. interlock register means having an output connected to an input of each of said first-named register means and having an input connected to an output of each of said first-named register means; and e. third control means associated with each of said data processors and connected to said interlock register means, said third control means being operable in response to process instructions from said first control means to selectively read binary coded information from selected register portions of the respective firstnamed register means to said interlock register means and being further operable in response to process instructions from said first control means to selectively write binary coded information into selected register portions oF the respective first-named register means from said interlock register means.

Claim 77

In a multiprocessor computer system having: a. memory means; b. a plurality of individual data processors connected to said memory means, said data processors having: i. X register means for storing data, said register means comprising a plurality of individually addressable register portions, ii. logic means connected to said register means for performing arithmetic, addressing and indexing functions, iii. instruction word register means adapted to receive instruction words from said memory means, iv. first control means responsive to instruction words from said instruction word register means for selectively operating said register portions to selectively read binary coded information from selected register portions to said logic means, and to selectively write binary coded information into selected register portions from said logic means, v. memory access control means for conditioning said memory means to transmit instruction words to said instruction word register means in accordance with predetermined access addresses, vi. address means connected to said memory access control means for generating said predetermined access addresses, said address means including program address register means providing program address indicative of individual data processing instructions of an object program, reference address register means providing a reference address unique to said object program, second control means responsive to said reference address and to said program address for adding said reference address to at least a portion of said program address, and gate means for selectively operating said second control means; vii. address stack means connected to said program address register means and containing one or more program addresses associated with instruction words stored in said instruction word register means, and means for applying data from said X register means to said program address register means; viii. out-of-stack means responsive to a non-coincidence between the data in said program address register means and the addresses in said address stack means for providing an enable signal; and ix. first select means responsive to said enable signal from said out-of-stack means for accepting data from said program address register means, said last-named data comprising first and second plurality of bits, said second control means including first adder means connected to said first select means for receiving said first plurality of bits, said first adder means being operable in response to operation of said gate means to binarily add said reference address to said first plurality of bits, said access control means being connected to said first adder means to receive the output from said adder means to receive the output from said adder means and said second plurality of bits; and c. input/output means operatively associated with said memory means; the improvement comprising: d. interlock register means having an output connected to an input of each of said first-named register means and having an input connected to an output of each of said first-named register means; and e. third control means associated with each of said data processors and connected to said interlock register means, said third control means being operable in response to process instructions from said first control means to selectively read binary coded information from selected register portions of the respective firstnamed register means to said interlock register means and being further operable in response to process instructions from said first control means to selectively write binary coded information into selected register portions oF the respective first-named register means from said interlock register means.

Claim 78

Apparatus according to claim 59 further including instruction fetch address means operable to receive data from said program address register means to forward said data to said first select means, and increment means for incrementally altering data in said instruction fetch address means to provide successive, incremental data.

Claim 79

Apparatus according to claim 70 further including exchange means providing an exchange address representative of the relative location in said memory means of an exchange routine outside of the field length of said object program, said exchange address being relative to said reference address, second select means responsive to said out-of-stack means for transferring said exchange address from said exchange means to said instruction fetch address means, incremental counter means associated with said exchange means for counting the number of transfers of data from said exchange means to said instruction fetch address means, and second adder means for adding the count in said counter means to data in said instruction fetch address means.

Claim 80

Apparatus according to claim 71 wherein said gate means includes an AND gate means having a first input connected to said reference address register means and a second input connected to receive an enable signal, said exchange means providing an enable signal for said AND gate.

Claim 81

Apparatus according to claim 72 wherein said gate means further includes OR gate means having a first input connected to receive an enable signal from said exchange means and having an output connected to the second input of said AND gate means, issue control means associated with said instruction word register means for issuing enable signals upon issuance of instructions of said object program, and means connecting the second input of said OR gate means to receive enable signals from said issue control means.