Sharing of microprograms between processors

Claim 2

In a multiprocessor system, the combination comprising: memory means for storing instructions of at least first and second programs; a first processor operating with a predetermined instruction set, said processor including a first control element for conditioning said processor to independently execute those instructions of said first program, said first control element including means for detecting instructions not within its instruction set and generating an out of set signal; a second processor operating with a different instruction set from said first processor, said second processor including a second control element for conditioning said second processor to execute independently instructions of said second program; and, logic means directly interconnecting said first and second control elements, said logic means in response to said out of set signal to condition said second control element to execute said out of set instruction sharing the same control facility said second processor uses to execute instructions of that kind occurring within its own program.

Claim 3

In a multiprocess system, the combination comprising: memory means for storing program instructions of at least first and second programs; a word processor operating with a predetermined instruction set and word data format, said processor including a first control element for conditioning said processor to independently execute those instructions of said first program, said word processor further including decoding means coupled to said first control element for trapping instructions specifying character orientEd operations and generating a trap control signal for conditioning said first control element to generate a call signal; a character processor operating with a different instruction set from said word processor and variable length data format, said second processor including a second control element to execute character oriented instructions of a second program; and, logic means directly interconnecting said first and second control elements, said logic means in response to said call control signal from said first control element to condition said second control element to execute the operations specified by said character oriented instructions sharing the same control facility said second processor uses to execute instructions of that kind occurring within its own program.

Claim 4

In a multiprocess system, the combination comprising: memory means for storing program instructions of at least first and second programs; a word processor operating with a predetermined instruction set and word data format, said processor including a first control element for conditioning said processor to independently execute those instructions of said first program, said word processor further including decoding means coupled to said first control element for trapping instructions specifying character orientEd operations and generating a trap control signal for conditioning said first control element to generate a call signal; a character processor operating with a different instruction set from said word processor and variable length data format, said second processor including a second control element to execute character oriented instructions of a second program; and, logic means directly interconnecting said first and second control elements, said logic means in response to said call control signal from said first control element to condition said second control element to execute the operations specified by said character oriented instructions sharing the same control facility said second processor uses to execute instructions of that kind occurring within its own program.

Claim 5

In a multiprocessor system, the combination comprising: memory means for storing instructions of at least two different program segments, said memory means comprising a plurality of memory locations, a predetermined number of which are used for interprocessor communications; a word processor operating with a predetermined instruction set and word data format, said processor including a first microprogrammed control element for conditioning said processor to independently execute those instructions of a first one of said program segments, said word processor further including decoding means for generating a trap control signal upon trapping an instruction specifying a character oriented operation executable by instructions not within its set, said first control element conditioned by said decoder trap signal to deposit a translated form of said trapped instruction in a predetermined one of said interprocessor communication storage locations and generate a first control signal; a character processor operating with a different instruction set from said word processor and variable length data format, said second processor including a second microprogrammed control element including a plurality of microprograms used by said second processor during its normal operaTion to execute character instructions of said second one of said program segments and a special microprogram sequence for simulating the normal extraction of a next instruction; and, mode control means directly interconnecting said first and second control elements, said mode control means responsive to said first control signal from said first microprogrammed control element to condition said second control element to switch said mode control means to a predetermined state, said second microprogrammed control element being conditioned by said mode control means when in said predetermined state to execute said special microinstruction sequence for fetching said instruction from said interprocessor communication storage location simultaneous with storing its previous state, said second processor being operative thereafter to branch a predetermined one of said microprograms for executing the operation specified by said translated instruction.

Claim 6

In a multiprocessor system, the combination comprising: memory means for storing instructions of at least two different program segments, said memory means comprising a plurality of memory locations, a predetermined number of which are used for interprocessor communications; a word processor operating with a predetermined instruction set and word data format, said processor including a first microprogrammed control element for conditioning said processor to independently execute those instructions of a first one of said program segments, said word processor further including decoding means for generating a trap control signal upon trapping an instruction specifying a character oriented operation executable by instructions not within its set, said first control element conditioned by said decoder trap signal to deposit a translated form of said trapped instruction in a predetermined one of said interprocessor communication storage locations and generate a first control signal; a character processor operating with a different instruction set from said word processor and variable length data format, said second processor including a second microprogrammed control element including a plurality of microprograms used by said second processor during its normal operaTion to execute character instructions of said second one of said program segments and a special microprogram sequence for simulating the normal extraction of a next instruction; and, mode control means directly interconnecting said first and second control elements, said mode control means responsive to said first control signal from said first microprogrammed control element to condition said second control element to switch said mode control means to a predetermined state, said second microprogrammed control element being conditioned by said mode control means when in said predetermined state to execute said special microinstruction sequence for fetching said instruction from said interprocessor communication storage location simultaneous with storing its previous state, said second processor being operative thereafter to branch a predetermined one of said microprograms for executing the operation specified by said translated instruction.

Claim 7

A data processing apparatus for extending the instruction set of at least one processor of a multiprocessor system, said multiprocessor system including at least first and second processors with different instruction sets, addressable memory storage means including a plurality of storage locations some of which store program instructions of at least first and second programs, said first processor including control means operative during the execution of instructions of said first program to trap instructions including operation codes not within its instruction set and generaTe a first external control signal, said data processing apparatus including said second processor and comprising: a microprogrammable control element being directly coupled to said control means, said control element including means for storing a plurality of microprograms referenced by said data processing apparatus during its execution of instructions of said second program and a first microinstruCtion sequence for simulating operations of the normal extraction of an instruction; and, program switching means including at least first and second states, said microprogrammable control element responsive to said external control signal for switching said program switching means from said first state to said second state, said switching means operative to condition said microprogrammable central element to switch said processor to a special mode wherein said control element generates a sequence of control signals from said first set of microinstructions which condition second processor to fetch said trapped instruction concurrent with storing the program state of said second processor and execute the operation specified by the operation code through one of the microprograms used for processing instructions of its own program, whereby said first processor is allowed to share all microprograms of said second processor.

Claim 8

A data processing apparatus for extending the instruction set of at least one processor of a multiprocessor system, said multiprocessor system including at least first and second processors with different instruction sets, addressable memory storage means including a plurality of storage locations some of which store program instructions of at least first and second programs, said first processor including control means operative during the execution of instructions of said first program to trap instructions including operation codes not within its instruction set and generaTe a first external control signal, said data processing apparatus including said second processor and comprising: a microprogrammable control element being directly coupled to said control means, said control element including means for storing a plurality of microprograms referenced by said data processing apparatus during its execution of instructions of said second program and a first microinstruCtion sequence for simulating operations of the normal extraction of an instruction; and, program switching means including at least first and second states, said microprogrammable control element responsive to said external control signal for switching said program switching means from said first state to said second state, said switching means operative to condition said microprogrammable central element to switch said processor to a special mode wherein said control element generates a sequence of control signals from said first set of microinstructions which condition second processor to fetch said trapped instruction concurrent with storing the program state of said second processor and execute the operation specified by the operation code through one of the microprograms used for processing instructions of its own program, whereby said first processor is allowed to share all microprograms of said second processor.

Claim 9

In a multiprocessing system comprising: memory storage means including a plurality of storage locations adapted for storing program instructions of at least two programs, at least two processors having different instruction repertoires, a first one of said processors including means for detecting an instruction not within its repertoire, each processor including a microprogrammed control element including a plurality of microprograms for independently executing instructions of at least one of said programs, and said system further including means for directly connecting at least one output of each microprogrammed control element as an input to the other microprogrammed control element and program switching means for switching one of said two processors between a normal mode and a special mode, said program switching means comprising; bistable storage means having at least first and second states, including an input circuit, and an output circuit, means connecting said bistable storage means to an output of the microprogrammed control element of the first one of said processors, said output circuit connected as another input of the microprogrammed control element of the second of said processors, said bistable means when in said first state operative to condition said second processor to operate in a normal mode wherein it executes instructions of its own program under the control of said microprogrammed control element, and said bistable means operative upon the receipt of a first control signal from said output in response to said microprogrammed element of said second processor being conditioned by said microprogrammed element of said first processor in response to detecting an instruction not within its repertoire, to be switched from said first state to said second state wherein said bistable means conditions said control element of said second processor to switch said processor to a special mode wherein said processor fetches a program instruction of said first processor and executes same using the same microprogram it normally uses to execute instructions of its own program.

Claim 10

In a multiprocessing system comprising: memory storage means including a plurality of storage locations adapted for storing program instructions of at least two programs, at least two processors having different instruction repertoires, a first one of said processors including means for detecting an instruction not within its repertoire, each processor including a microprogrammed control element including a plurality of microprograms for independently executing instructions of at least one of said programs, and said system further including means for directly connecting at least one output of each microprogrammed control element as an input to the other microprogrammed control element and program switching means for switching one of said two processors between a normal mode and a special mode, said program switching means comprising; bistable storage means having at least first and second states, including an input circuit, and an output circuit, means connecting said bistable storage means to an output of the microprogrammed control element of the first one of said processors, said output circuit connected as another input of the microprogrammed control element of the second of said processors, said bistable means when in said first state operative to condition said second processor to operate in a normal mode wherein it executes instructions of its own program under the control of said microprogrammed control element, and said bistable means operative upon the receipt of a first control signal from said output in response to said microprogrammed element of said second processor being conditioned by said microprogrammed element of said first processor in response to detecting an instruction not within its repertoire, to be switched from said first state to said second state wherein said bistable means conditions said control element of said second processor to switch said processor to a special mode wherein said processor fetches a program instruction of said first processor and executes same using the same microprogram it normally uses to execute instructions of its own program.

Claim 11

A multiprocessor system comprising: memory means comprising a plurality of memory modules each comprising a plurality of memory storage locations, groups of said memory locations of predetermined ones of said memory modules assigned to store instructions of a different one of a plurality of programs and one of said memory modules including a predetermined number of fixed storage locations assigned for interprocessor communications; a first multiprogrammed processor operating with a predetermined instruction set, said processor including a first microprogrammed control element for conditioning said processor to independently execute instructions for a number of said plurality of programs, each program being designated by a group coded and assigned a different memory protection code, one of said programs being assigned a master control function for said system, said first processor further including a multiprogrammed traffic control means for scanning eacH of said programs and assigning cycles to active ones of said programs; a second processor operating with a different instruction set, said processor including a second microprogrammed element for storing a plurality of microprograms used by said processor during its normal operaTion to execute instructions of at least one of said plurality of programs and a first special control sequence for executing operations which simulate a normal extraction of an instruction; said first processor further including decoding means connected to said first control means and being operative to trap operation codes of instructions not executable by said programs, said control means being conditioned by a trapped control signal from said decoder means to condition said first control element to transfer program control from the program originating said trapped instruction to said master program, said first control element being operative to execute a sequence of operations specified by said master program to translate each of said trapped instructions into an instruction including an operation code executable by said second processor in addition to address information pertinent to referencing the area of memory assigned to said originating program and then to store said translated instruction in an appropriate one of said communication storage locations; and, means directly interconnecting said first and second microprogrammed control elements, said means responsive to a signal from said first control element to condition said second control element for having said second processor enter a special mode wherein said processor executes said special control sequence wherein it fetches said translated instruction from said communications storage location simultaneously with storing information pertinent for returning to the program being executed by said second processor, said second control element being conditioned by the opcode of said translated instruction to reference one of the microprograms normally referenced by said processor to execute like operations specified by instructions of its own programs.

Claim 12

A multiprocessor system comprising: memory means comprising a plurality of memory modules each comprising a plurality of memory storage locations, groups of said memory locations of predetermined ones of said memory modules assigned to store instructions of a different one of a plurality of programs and one of said memory modules including a predetermined number of fixed storage locations assigned for interprocessor communications; a first multiprogrammed processor operating with a predetermined instruction set, said processor including a first microprogrammed control element for conditioning said processor to independently execute instructions for a number of said plurality of programs, each program being designated by a group coded and assigned a different memory protection code, one of said programs being assigned a master control function for said system, said first processor further including a multiprogrammed traffic control means for scanning eacH of said programs and assigning cycles to active ones of said programs; a second processor operating with a different instruction set, said processor including a second microprogrammed element for storing a plurality of microprograms used by said processor during its normal operaTion to execute instructions of at least one of said plurality of programs and a first special control sequence for executing operations which simulate a normal extraction of an instruction; said first processor further including decoding means connected to said first control means and being operative to trap operation codes of instructions not executable by said programs, said control means being conditioned by a trapped control signal from said decoder means to condition said first control element to transfer program control from the program originating said trapped instruction to said master program, said first control element being operative to execute a sequence of operations specified by said master program to translate each of said trapped instructions into an instruction including an operation code executable by said second processor in addition to address information pertinent to referencing the area of memory assigned to said originating program and then to store said translated instruction in an appropriate one of said communication storage locations; and, means directly interconnecting said first and second microprogrammed control elements, said means responsive to a signal from said first control element to condition said second control element for having said second processor enter a special mode wherein said processor executes said special control sequence wherein it fetches said translated instruction from said communications storage location simultaneously with storing information pertinent for returning to the program being executed by said second processor, said second control element being conditioned by the opcode of said translated instruction to reference one of the microprograms normally referenced by said processor to execute like operations specified by instructions of its own programs.

Claim 13

The system of claim 6 wherein said first multiprogrammed processor further includes a memory means comprising a plurality of storage locations for storing said key codes and base addresses for each of said programs, and wherein said master program directs said first control element during said translation of said trapped instruction to reference the key register and base register assigned to said originating program and insert the contents thereof into said communication storage location as part of said translated instruction for transfer to said second processor.

Claim 14

The system of claim 6 wherein said trapped instruction is coded as a privileged instruction, and said master program directs said first control element to translate the opcode of said privileged instruction into an appropriate one of the opcodes within the repertoire of said second processor.

Claim 15

The system according to claim 5 wherein said first processor is a word oriented processor having a word data format and said second processor is a character oriented processor having a variable length data format.

Claim 16

The system according to claim 8 wherein said opcodes of said translated instructions are within the class of opcodes which specify character oriented operations.

Claim 17

The system of claim 6 wherein said translated instruction includes control information associated with said originating program for allowing said second processor to access those areas of memory assigned to said originating program during execution of said translated instruction.

Claim 18

The system according to claim 11 wherein said control information includes a key code and base address code.

Claim 19

The system of claim 6 wherein said memory means is protected by a system of lock and key codes, said second processor further including a memory store comprising a plurality of memory storage locations for storing a number Of lock codes assigned to a corresponding number of memory blocks to which said second processor has access; said second processor further including a key register for storing a key protection code assigned to the program being executed by said second processor, said second microprogrammed control element preliminary to the execution of said translated instruction being operative to execute said first special control sequence, store the contents of said key to register and load said register with a key code assigned to said originating program contained within said translated instruction for comparing the key register contents to a lock code associated with addressed memory locations for determining whether said second processor has been previously granted access hereto.

Claim 20

The system of claim 13 wherein said second processor further includes means for generating a first signal when both of said key codes compare equally and a write inhibit second signal when both codes do not compare equally for inhibiting writing into the memory storage location being addressed, and said second microprogram control element including a further microinstruction control sequence, said second control element being conditioned by said write inhibit signal to reference said further microinstruction sequence for signaling said first control element and said master program of a write violation.

Claim 21

The system of claim 13 wherein said second processor further includes a base register, said microprogrammed control element during the execution of said special control sequence in addition to storing said key code, stores the base address code contents of said base register of said program and said base register with the base address assigned to said originating program for comparing said key register contents with lock codes associated with base relocated memory address locations.

Claim 22

A system according to claim 6 wherein said first processor further comprises address generating means and arithmetic and logic means, said address generating means comprising a microprogram control element for providing microinstructions for directing the operations of said address generator and said arithmetic and logic means comprising a second microprogram control element for providing microinstructions for directing the operations of said arithmetic means whereby said address generating means and said arithmetic and logic means operate concurrently during the processing of instructions of said plurality of active programs.

Claim 23

The system according to claim 6 wherein said first processor further includes a control memory having a plurality of memory groups, each of which comprises a plurality of memory storage locations, said multiprogrammed traffic control means connected to said control memory to select storage locations within different ones of said groups in accordance with programs that are active.

Claim 24

The system of claim 6 wherein said interconnecting means includes a call line and a response line for signaling respectively a request for a microprogram of said second processor and the completion of microprogram execution of said microprogram requested.

Claim 25

The system of claim 6 wherein said microprogrammed control element of said second processor further stores a control sequence for causing said element to generate an external response signal upon completing the execution of said microprogram simultaneous with causing said second processor to execute operations for the restoring of said information pertinent to returning to said program it was previously executing.

Claim 26

In a multiprocessor system, the method of extending the instruction set of a first processor by sharing microprograms between at least one other processor of said system, said method comprising the steps: storing a plurality of microprograms in microprogrammed control elements individually associated with each of said two processors for controlling the execution of different types of program instRuctions within said two processors; generating in response to the operation code of each of those instructions of a program assigned to said first of said two processors which are to be executed by sharing microprograms stored in the microprogrammed control element of a second of said two processors, a first control signal to trap each said instruction and for conditioning said microprogrammed control element to sequence through a microinstruction sequence including a predetermined microinstruction word coded to generaTe an external control signal therefrom: generating first and second sets of control signals from first and second microinstruction sequences stored at predetermined points within the microprogrammed control element of said second processor, said first set of said signals of said first sequence being used to simulate a normal instruction FETCH to fetch said trapped instruction and simultaneous store the machine state of its processor, said first sequence being coded to merge with said plurality of microprograms stored within said microprogrammed control element, said second set of control signals of said second sequence being used to restore said machine state and simultaneously generate a response signal to said first processor signaling the completion of microprogram execution; and sensing said external control signal applied to the control element of said second processor, and conditioning said control element to generate said first and second sets of signals to execute said first sequence, and said second sequence after said processor executes a microprogram selected through the operation code of said trapped instruction which is normally used to execute like operations specified by instructions of its own program.

Claim 27

In a multiprocessor system, the method of extending the instruction set of a first processor by sharing microprograms between at least one other processor of said system, said method comprising the steps: storing a plurality of microprograms in microprogrammed control elements individually associated with each of said two processors for controlling the execution of different types of program instRuctions within said two processors; generating in response to the operation code of each of those instructions of a program assigned to said first of said two processors which are to be executed by sharing microprograms stored in the microprogrammed control element of a second of said two processors, a first control signal to trap each said instruction and for conditioning said microprogrammed control element to sequence through a microinstruction sequence including a predetermined microinstruction word coded to generaTe an external control signal therefrom: generating first and second sets of control signals from first and second microinstruction sequences stored at predetermined points within the microprogrammed control element of said second processor, said first set of said signals of said first sequence being used to simulate a normal instruction FETCH to fetch said trapped instruction and simultaneous store the machine state of its processor, said first sequence being coded to merge with said plurality of microprograms stored within said microprogrammed control element, said second set of control signals of said second sequence being used to restore said machine state and simultaneously generate a response signal to said first processor signaling the completion of microprogram execution; and sensing said external control signal applied to the control element of said second processor, and conditioning said control element to generate said first and second sets of signals to execute said first sequence, and said second sequence after said processor executes a microprogram selected through the operation code of said trapped instruction which is normally used to execute like operations specified by instructions of its own program.

Claim 28

In a multiprocessor system, the method of extending the instruction set of a first processor by sharing microprograms stored in the microprogrammed control element of at least one other processor of said system whose instruction set is different from that of said first processor, said method comprising the steps of: generating in response to the operation code of each of those instructions of a program assigned to said first processor which are to be executed by said other processor a first control signal to trap each said instruction and to condition said microprogrammed control element to sequence through a predetermined microinstruction sequence which generates an external control signal; generating in response to said external control signal a first set of control signals from a first special microinstruction sequence stored at a predetermined point within said microprogrammed control element of said second processor, said first set of signals for conditioning said other processor to fetch each said trapped instruction and concurrently store the machine state of said other processor; and, said special sequence conditioning said processor to sequence to a point common to said microprograms stored therein and thereafter causing the selection of a microprogram to perform the operation designated by said trapped instruction which said other processor uses to execute like operations specified by instructions within its own program.

Claim 29

In a multiprocessor system, the method of extending the instruction set of a first processor by sharing microprograms stored in the microprogrammed control element of at least one other processor of said system whose instruction set is different from that of said first processor, said method comprising the steps of: generating in response to the operation code of each of those instructions of a program assigned to said first processor which are to be executed by said other processor a first control signal to trap each said instruction and to condition said microprogrammed control element to sequence through a predetermined microinstruction sequence which generates an external control signal; generating in response to said external control signal a first set of control signals from a first special microinstruction sequence stored at a predetermined point within said microprogrammed control element of said second processor, said first set of signals for conditioning said other processor to fetch each said trapped instruction and concurrently store the machine state of said other processor; and, said special sequence conditioning said processor to sequence to a point common to said microprograms stored therein and thereafter causing the selection of a microprogram to perform the operation designated by said trapped instruction which said other processor uses to execute like operations specified by instructions within its own program.