US3760365A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiprocessing computing system with task assignment at the instruction level
Assignee: International Business Machines Corp
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Filing: 1971-12-30
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Granted: 1973-09-18
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Expires: 1991-12-30
Abstract
Abstract The present invention relates to a multiprocessing system wherein job assignments to the respective processors are made at the level of very small tasks. Further, the system is organized so that none of the multiprocessing capabilities need be known either to the programmer or to a supervisory program. Task assignment is done at the instruction level. By instruction level is meant a typical computer''s machine language. In the disclosed embodiment, two processors are shown; however, it is to be understood that the basic concepts of the present invention could well be extended to more than two processors. Each of these processors shares a main store, a microinstruction store and a local store. Further, automatic control of the two systems is performed with the use of a set of shared latches to prevent one of the processors from interfering with another, with resulting erroneous results. Maximum availability of the system is assured since the system may operate either in the multiprocessing mode or, in the event that one of the processors should fail, the other processor can continue operating completely autonomously.
Inventors
- 👤 R Villani
- 👤 J Kurtzberg
- 👤 J Rosenfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/52
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
145 words
A multi-processor computing system for processing a single machine language instruction list comprising: a plurality of separate processor elements, each processor element having a separate control means for providing sequences of instructions to its associated processor for execution; a common storage means accessible to each of said plurality of processor elements; each control means including means for sharing said common storage means, and a plurality of interlocks for preventing unwanted interaction among said plurality of processors; each said control means further including means for initiating control sequences controllng the operation of each of said processors; each said control means further including means for accessing successive machine language instructions from said storage means submitted to said multiprocessing system for execution; and said initiating means including means for converting each machine language instruction into actual electrical signal sequences suitable for the direct control of the associated processor.
Claim 2
Dependent Claim
145 words
A multi-processor computing system for processing a single machine language instruction list comprising: a plurality of separate processor elements, each processor element having a separate control means for providing sequences of instructions to its associated processor for execution; a common storage means accessible to each of said plurality of processor elements; each control means including means for sharing said common storage means, and a plurality of interlocks for preventing unwanted interaction among said plurality of processors; each said control means further including means for initiating control sequences controllng the operation of each of said processors; each said control means further including means for accessing successive machine language instructions from said storage means submitted to said multiprocessing system for execution; and said initiating means including means for converting each machine language instruction into actual electrical signal sequences suitable for the direct control of the associated processor.
Claim 3
Dependent Claim
56 words
A multi-processor computing system as set forth in claim 1 wherein said control means further includes means for sharing a micro-instruction store, said micro-instruction store containing the actual control sequences for controlling the operation of each of said processors, and said means for converting including means for decoding said micro-instructions to produce said multi-processor control signals.
Claim 4
Dependent Claim
48 words
A multi-processor computing system as set forth in claim 2 wherein said common storage means includes a separately accessible main storage and a separately accessible local storage and wherein interlock means are provided whereby only one processor may access either of said storage means at any one time.
Claim 5
Dependent Claim
57 words
A multi-processor computing system as set forth in claim 1 wherein said control means includes means for sequentially accessing said single machine language instruction list for the next unaccessed instruction therein each time the associated processor has completed a current instruction from said list whereby instructions are accessed by a given processor on a ''''first-come-first served'''' basis.
Claim 6
Dependent Claim
153 words
A multi-processor computing system comprising: a plurality of separate processor elements, each processor element having a separate control means for providing sequences of instructions to its associated processor for execution; a main storage means accessible to each of said plurality of separate processors; each control means including means for sharing said main storage, a local storage, and a plurality of interlocks for preventing unwanted interaction among said plurality of processors; each said control means further including means for sharing a micro-instruction store, said micro-instruction store containing the actual control sequences for controlling the operation of each of said processors; each said control means further including means for accessing successive machine language instructions from a system instruction list stored in said main storage which are submitted to said multiprocessing system for execution; and means for converting said machine language instructions into micro-instruction sequences suitable for direct execution on one of said plurality of processors.
Claim 7
Dependent Claim
153 words
A multi-processor computing system comprising: a plurality of separate processor elements, each processor element having a separate control means for providing sequences of instructions to its associated processor for execution; a main storage means accessible to each of said plurality of separate processors; each control means including means for sharing said main storage, a local storage, and a plurality of interlocks for preventing unwanted interaction among said plurality of processors; each said control means further including means for sharing a micro-instruction store, said micro-instruction store containing the actual control sequences for controlling the operation of each of said processors; each said control means further including means for accessing successive machine language instructions from a system instruction list stored in said main storage which are submitted to said multiprocessing system for execution; and means for converting said machine language instructions into micro-instruction sequences suitable for direct execution on one of said plurality of processors.
Claim 8
Dependent Claim
66 words
A multi-processor computing system as set forth in claim 5 wherein said means for converting machine language instructions into microprogram sequences includes means for accessing a particular field of said machine language instruction and deriving an address in said micro-instruction store, and means for utilizing said address as an entry point into a micro-instruction sequence for performing the operation called for in said machine language instruction.
Claim 9
Dependent Claim
41 words
A multi-processor computing system as set forth in claim 6 including means for determining if all or only part of an accessed machine language instruction can be performed immediately or must await the performance of some part of a previous instruction.
Claim 10
Dependent Claim
73 words
A multi-processor computer system as set forth in clAim 5 wherein at least some of said shared interlocks comprise hardware latches; said control means include means for testing and setting each of said latches under appropriate microinstruction control; means for preventing a given processor control means from proceeding with a particular operation when a particular one of said latches is set to a predetermined condition whereby unwanted interaction between said processors is prevented.
Claim 11
Dependent Claim
49 words
A multi-processor computing system as set forth in claim 8 including means for both testing and setting an interlock in a single processor cycle whereby an erroneous test for a latch condition cannot be made by another processor before said latch can be set by the first testing processor.
Claim 12
Dependent Claim
57 words
A multi-processor computer system as set forth in claim 9 wherein said control means for each processor includes means for sequentially accessing successive unaccessed machine language instructions from memory each time the associated processor has completed a current instruction whereby one processor may perform a number of successive instructions while another processor is performing a single instruction.
Claim 13
Dependent Claim
139 words
A multi-processor computer system as set forth in claim 10 said control means for each processor including means for preventing a processor from proceeding with a task requiring any operands which are to be obtained from a previous instruction until such operands are available, said means including means for setting an availablilty bit in a specified register which is designated for holding the results of such previous operations wherein the same register is designated in the subsequent operation when the result of the preceding operation is to be used as an operand in a subsequent operation, said availability bit being tested by the control means associated with a given processor before any given operation is performed, and means for suspending operation of that processor until the availablility bit of the specified register is set to a predetermined ''''go-ahead'''' condition.
Claim 14
Dependent Claim
38 words
A multi-processor computer system as set forth in claim 10, said control means including further means for prohibiting its associated processor from accessing an instruction stored in said main storage means which may be altered by another processor.
Claim 15
Dependent Claim
57 words
A multi-processor computer system as set forth in claim 11, wherein each control means for each processor further includes means associated with said main store for preventing its associated processor from accessing an operand address therein which address is to be used by another processor currently executing a store instruction, precedent in time to the current instruction.
Claim 16
Dependent Claim
73 words
A multi-processor computer system as set forth in claim 10, wherein said control means includes means for prohibiting the testing and setting of condition-indicating data in the wrong sequence, said means including interlocks whereby if an operation is currently affecting said condition-indicating data, said data cannot be accessed by another operation logically subsequent to the one currently being performed until said current operation has an opportunity to modify the condition data as required.
Claim 17
Dependent Claim
54 words
A multi-processor computer system as set forth in claim 14 wherein said condition indicating data comprises a condition code data field, and interlock means are provided to prevent a subsequent operation from accessing said condition code before an operation currently undergoing execution has finished with the instruction at least implicitly modifying said condition code.
Claim 18
Dependent Claim
70 words
A multi-processor computer system as set forth in claim 14 wherein said condition containing data comprises a condition code field accompanying other data, said means for preventing the improper altering of said condition code including means for preventing the testing of the current state of said condition code by a given processor before a processor currently executing an instruction at least implicitly modifying said condition code hAs completed said instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-17 | 1977-03-19 | 1977-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-17 | 1981-03-19 | 1981-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-17 | 1985-03-19 | 1985-09-18 | $7700.00 | Window Closed / Lapsed |