Circuitry for detecting faults in duplicate controllers

Claim 2

Fault detector circuitry for first and second system controllers and means alternately connecting each one of said controllers individually to peripheral system circuits at prescribed intervals for active and standby control of system operation, said detector circuitry comprising means for decrementally and incrementally counting trouble signals from connected active ones of said controllers, means responsive to said counting to prescribed decremental and incremental count states of said counting means for identifying a faulty one of said controllers, and means activated by said identifying means for controlling said connecting means to switch a faulty one of said controllers into a standby control state.

Claim 3

The invention of claim 1 further comprising means activated by said connecting means for steering said trouble signals from each connected one of said controllers to said counting means, said counting means having means controlled by said connecting means for decrementally and incrementally counting said trouble signals received through said steering means from said first and said second controllers.

Claim 4

The invention of claim 1 further comprising counter means for counting controller successful operation signals, means controlled by said connecting means for steering said operation signals from each connected one of said controllers to said counter means, and means responsive to a predetermined count state of said counter means for periodically operating said counting means to a reference count state between said prescribed decremental and incremental count states thereof.

Claim 5

Fault detector circuitry for first and second system controllers and means alternately connecting each one of said controllers individually to peripheral system circuits at prescribed intervals for active and standby control of system operations, said connecting means being operable for locking either of said controllers into a standby control state, said detector circuitry comprising bidirectional counter means having a prescribed initial midpoint count state and being responsive to trouble signals from said controllers under control of said connecting means for decrementally counting said trouble signals from a connected said first controller and counting incrementally said trouble signals from a connected said second controller to provide a continuous comparative indication of the integrity of each of said first and second controllers, means for counting signals signifying completed work operations of connected ones of said controllers, means reSponsive to a prescribed count state of said counting means for periodically reinitializing said bidirectional counter means to said midpoint count state, means for detecting the presence of prescribed lower and upper count states of said bidirectional counter means identifying preferred and nonpreferred ones of said first and second controllers, and means activated by said detecting means for operating said connecting means to lock a nonpreferred one of said controllers into said standby control state.

Claim 6

Fault detector circuitry for first and second system controllers and means alternately connecting each one of said controllers individually to peripheral system circuits at prescribed intervals for active and standby control of system operations, said connecting means being operable for locking either of said controllers into a standby control state, said detector circuitry comprising bidirectional counter means having a prescribed initial midpoint count state and being responsive to trouble signals from said controllers under control of said connecting means for decrementally counting said trouble signals from a connected said first controller and counting incrementally said trouble signals from a connected said second controller to provide a continuous comparative indication of the integrity of each of said first and second controllers, means for counting signals signifying completed work operations of connected ones of said controllers, means reSponsive to a prescribed count state of said counting means for periodically reinitializing said bidirectional counter means to said midpoint count state, means for detecting the presence of prescribed lower and upper count states of said bidirectional counter means identifying preferred and nonpreferred ones of said first and second controllers, and means activated by said detecting means for operating said connecting means to lock a nonpreferred one of said controllers into said standby control state.

Claim 7

The invention of claim 4 further comprising logic means controlled by said connecting means for steering said trouble signals from each connected one of said controllers to said counter means, said counter means having a decremental count mode activated by said connecting means for a connected said first controller and an incremental count mode activated by said connecting means for a connected said second controller for counting said trouble signals received from said steering logic means.

Claim 8

The invention of claim 4 further comprising logic means controlled by said connecting means for steering said completed work operation signals from each connected one of said controllers to said counting means.

Claim 9

The invention of claim 4 wherein said operating means comprises means activated by said detecting means in cooperation with receipt of one of said completed work operation signals for storing an identifying indication of a detected one of said lower and upper count states present in said counter means, and an activation of said storing means being effective for controlling operations of said connecting means to lock said nonpreferred one of said controllers identified by said stored indication into said standby control state.

Claim 10

The invention of claim 7 further comprising means responsive to activation of said operating means for preserving detected ones of said lower and upper count states in said counter means to maintain activation of said operating means.

Claim 11

The invention of claim 8 wherein said preserving means comprises logic means enabled by activation of said storing means for inhibiting said trouble signal inputs to said counter means, and other logic means enabled by activation of said storing means for inhibiting said completed work operation signal inputs to said counting means to prevent reinitializing of said counter means to said midpoint count state.

Claim 12

The invention of claim 9 further comprising means manually operated for setting said counter means to said midpoint count state to restore alternate connecting operations of said connecting means.

Claim 13

Circuitry for detecting faults in first and second system controllers and means for connecting said controllers individually to peripheral circuits for active and standby control of said peripheral circuits, said circuitry comprising means for periodically interchanging active and standby ones of said controllers by controlling operations of said connecting means, bidirectional counter means having a prescribed initial count state and being responsive for counting from said initial count state decrementally trouble signals from an active said first controller and incrementally trouble signals from an active said second controller, means for detecting prescribed count states of said counter means decrementally and incrementally removed from said initial count state and signifying a faulty one of respective said first and said second controllers, and control means responsive to said detecting means when activated for controlling operations of said interchanging means to switch said faulty one of said controllers into a standby control state.

Claim 14

Circuitry for detecting faults in first and second system controllers and means for connecting said controllers individually to peripheral circuits for active and standby control of said peripheral circuits, said circuitry comprising means for periodically interchanging active and standby ones of said controllers by controlling operations of said connecting means, bidirectional counter means having a prescribed initial count state and being responsive for counting from said initial count state decrementally trouble signals from an active said first controller and incrementally trouble signals from an active said second controller, means for detecting prescribed count states of said counter means decrementally and incrementally removed from said initial count state and signifying a faulty one of respective said first and said second controllers, and control means responsive to said detecting means when activated for controlling operations of said interchanging means to switch said faulty one of said controllers into a standby control state.

Claim 15

The invention of claim 11 further comprising means controlled by said connecting means for steering said trouble signals only from each active one of said controllers to said bidirectional counter means, said bidirectional counter means having counting modes controlLed by said interchanging means for decrementally and incrementally counting said trouble signals from said respective first and said second controllers to provide over successive ones of said time intervals a comparative indication of the relative integrity of each of said controllers.

Claim 16

The invention of claim 11 further comprising means for counting signals signifying completed operations of each active one of said controllers, means controlled by said connecting means for steering said completion signals only from each active one of said controllers to said counting means, and means responsive to a prescribed count state of said counting means for periodically activating said bidirectional counter means to said initial count state.

Claim 17

The invention of claim 11 wherein said interchanging means comprises means operable for defining active and standby ones of said controllers, and means for periodically operating said defining means after expiration of prescribed time intervals to cause said connecting means to switch active and standby ones of said controllers.

Claim 18

The invention of claim 14 wherein said means for operating said defining means comprises means for generating said prescribed time intervals, means activated by said generating means after expiration of one of said time intervals in cooperation with a receipt of a signal signifying a completed operation of an active one of said controllers for initiating an active and standby controller switching operation of said defining means, wherein said generating means is responsive to an activation of said initiating means for causing said generating means to generate another one of said prescribed time intervals.

Claim 19

The invention of claim 14 wherein said control means comprises means activated by said detecting means for storing the identity of a detected one of said prescribed count states, said activated storing means being effective for locking operated said defining means to preclude further switching of said faulty one of said controllers from a standby status.

Claim 20

A circuit connectable to first and second private branch exchange system controllers for detecting faults in said controllers comprising flip-flop circuitry for defining active and standby ones of said first and second controllers, and being operable for alternating active and standby ones of said controllers and further operable for locking a faulty one of said controllers in a standby control state, a transfer relay operated and released under control of said flip-flop circuitry and having means for connecting each one of said controllers individually to peripheral circuits, timing means for generating successive predetermined time intervals, means activated in response to concurrence of expiration of one of said time intervals and a receipt of a signal signifying completed mode operations of the then active one of said controllers for operating said flip-flop circuitry in an absence of a prescribed number of faults in said active one of said controllers to alternate said active and standby ones of said controllers, means activated concurrently with operation of said flip-flop circuitry for operating said timing means to generate another one of said predetermined time intervals, a bidirectional counter having a prescribed initial midpoint count state and decremental and incremental counting modes controlled by said flip-flop circuitry for counting trouble signals signifying noncompleted operations of each active one of said controllers decrementally when said first controller is active and incrementally when said second controller is active, means controlled by contacts of said relay for steering said trouble signals only from each active one of said controllers to said counter, a mode completion counter for counting said completed mode operation signals from each active one of said controllers, means controlled by other contacts of said relay For steering said completed operation signals only from each active one of said controllers to said mode completion counter, means activated by a prescribed count state of said mode completion counter for periodically reinitializing said bidirectional counter to said midpoint count state, means for detecting prescribed lower and upper count states of said bidirectional counter indicating a faulty one of said first and said second controllers, storage means activated by said detecting means for operating said flip-flop circuitry to lock a faulty active one of said controllers identified by a detected one of said lower and upper count states into said standby state, logic means enabled by activation of said storage means for preserving said detected one of said lower or upper count states in said bidirectional counter to maintain activation of said storage means, and switch means operable for manually reinitializing said bidirectional counter to said midpoint count state to remove locked control of said flip-flop circuitry to restore alternating operations of said active and standby ones of said controllers.

Claim 21

A circuit connectable to first and second private branch exchange system controllers for detecting faults in said controllers comprising flip-flop circuitry for defining active and standby ones of said first and second controllers, and being operable for alternating active and standby ones of said controllers and further operable for locking a faulty one of said controllers in a standby control state, a transfer relay operated and released under control of said flip-flop circuitry and having means for connecting each one of said controllers individually to peripheral circuits, timing means for generating successive predetermined time intervals, means activated in response to concurrence of expiration of one of said time intervals and a receipt of a signal signifying completed mode operations of the then active one of said controllers for operating said flip-flop circuitry in an absence of a prescribed number of faults in said active one of said controllers to alternate said active and standby ones of said controllers, means activated concurrently with operation of said flip-flop circuitry for operating said timing means to generate another one of said predetermined time intervals, a bidirectional counter having a prescribed initial midpoint count state and decremental and incremental counting modes controlled by said flip-flop circuitry for counting trouble signals signifying noncompleted operations of each active one of said controllers decrementally when said first controller is active and incrementally when said second controller is active, means controlled by contacts of said relay for steering said trouble signals only from each active one of said controllers to said counter, a mode completion counter for counting said completed mode operation signals from each active one of said controllers, means controlled by other contacts of said relay For steering said completed operation signals only from each active one of said controllers to said mode completion counter, means activated by a prescribed count state of said mode completion counter for periodically reinitializing said bidirectional counter to said midpoint count state, means for detecting prescribed lower and upper count states of said bidirectional counter indicating a faulty one of said first and said second controllers, storage means activated by said detecting means for operating said flip-flop circuitry to lock a faulty active one of said controllers identified by a detected one of said lower and upper count states into said standby state, logic means enabled by activation of said storage means for preserving said detected one of said lower or upper count states in said bidirectional counter to maintain activation of said storage means, and switch means operable for manually reinitializing said bidirectional counter to said midpoint count state to remove locked control of said flip-flop circuitry to restore alternating operations of said active and standby ones of said controllers.