Automatic telecommunication switching system and information handling system

Claim 2

Automatic telecommunication switching system comprising: a switching network and a programmed control system for said switching network; said control system including at least two identical and equal status pRogrammed processors which simultaneously and actively control the whole of said network; transmission means for transmitting information concerning communication control operations performed in said switching network by each one of said processors to at least one of the other processors, said transmitted information enables said other processor to further handle the communication control operations previously undertaken by each said one processor when the latter becomes faulty; and each said processor includes memory means to store information words regarding communication control operations and each information word contains an indication of the processor handling the corresponding communication control operation each processor normally using only the words associated thereto.

Claim 3

Automatic telecommunication switching system according to claim 1 wherein when a said one processor becomes faulty each of said other processors starts a takeover operation, the system including means for interrogating its said memory means to detect the words stored therein with an indication that they concern communication control operations handled by the faulty processor and means for taking over these communication control operations by means of the information stored in these words.

Claim 4

Automatic telecommunication switching system according to claim 2 wherein said information transmitted prevents said other processor from performing the communication control operations undertaken by each said one processor during its normal operation.

Claim 5

Automatic telecommunication switching system according to claim 3 in which said transmitted information includes identities of circuits involved in said communication control operations, and said transmitted information includes orders to be executed in circuits to be found in said other processor by means of said identities.

Claim 6

Automatic telecommunication switching system according to claim 4 in which said transmitted information includes data to be inscribed in said circuits found under control of said orders, and said data concerns the phase at which the processing of said communication control operations has arrived.

Claim 7

Automatic telecommunication switching system according to claim 5 in which a said communication control operation performed in said switching network by a said one processor includes means to control a call connection between calling and called stations through a junctor and other switching means of said switching network, each such means to control a call connection include a register phase during which said connection is established, a conversation phase during which said connection is maintained and a release phase during which said connection is released.

Claim 8

Automatic telecommunication switching system according to claim 6 wherein said information words of a processor are each permanently associated to a said junctor involved in a call connection, and when the identity of a said junctor and the indicatives of said register phase or of said conversation phase are received together with accompanying orders, the orders control the finding of the finding of the corresponding information word by means of this identity as well as the storage therein of said indicatives.

Claim 9

Automatic telecommunication switching system according to claim 6 wherein said information words of a processor are each permanently associated to a said junctor involved in a call connection and that when the identity of a said junctor and the indicative of said release phase are received together with accompanying orders, said orders control the finding of the corresponding information word by means of this identity as well as the erasing of this information work.

Claim 10

Automatic telecommunication switching system according to claim 6 in which said memory means of a processor store a plurality of second information words each including one or more bits and each permanently associated to a said station involved in a call connection and that when The identity of a said station is received together with accompanying orders, said orders control the finding of the corresponding second information word by means of said identity as well as the setting of this second information word in a condition indicating that the corresponding station is busy.

Claim 11

Automatic telecommunication switching system according to claim 9 wherein each said other processor, after having detected the first words stored therein with an indication that they concern connection control operations handled by the faulty processor, read these words in order to find what processing state these call connections have reached and processes these call connections further depending on the phase read; each said other processor releases all the call connections which are found in their register phase; and each said other processor maintains all the call connections which are found in their conversation phase and modifies for each call connection maintained the indication that the call connection control operation is handled by said one processor in order that it should now indicate that the call connection control operation is handled by said other processor.

Claim 12

Automatic telecommunication switching system according to claim 9 in which said memory means of each processor store plurality of third information words each permanently associated to an input of said junctor and each of which stores the condition of the loop between the associated junctor input and a said station involved in a call connection, and said other processor sets all the third information words associated to junctors involved in call connections which are found in their conversation phase in a condition indicating that the corresponding loop is closed irrespective of the actual state thereof.

Claim 13

Automatic telecommunication switching system according to claim 1 including fault detection means comprising means for counting the number of calls treated in each processor, means for comparing the respective numbers counted by any two processors, and means for indicating as faulty to the other processor that processor which has counted the smaller number of calls treated, when the difference between said numbers reaches a predetermined value for a given maximum value of said numbers.

Claim 14

Automatic telecommunication switching system according to claim 12 wherein each processor includes fault detection means comprising a first accumulator adapted to count the difference between the number of calls treated by the two processors, the number of the other processor being coupled by said transmission means, and a second accumulator adapted to count the number of calls treated by one of said two processors, whereby said fault detection means react to said first accumulator reaching a first or a second predetermined value, when said second accumulator has not exceeded a third predetermined value, to indicate that one or the other processor is faulty.

Claim 15

Automatic telecommunication switching system according to claim 1 including fault detection means comprising means for comparing the number of transmissions of said information from one processor to another processor with the number of transmissions of said information from said other processor to said one processor and for indicating as faulty to the other processor that processor which originates the smaller number of transmission, when the difference between said numbers reaches a predetermined value for a given maximum value of said numbers.

Claim 16

Automatic telecommunication switching system according to claim 14 wherein said fault detection means includes a reversible first counter with two inputs and a second and third unidirectional counter with one input, said first counter being able to count in each direction said predetermined first value and said second and third counters being able to count a second predetermined value which is larger than the first predetermined value, said one processor is connected to one input of said first counter and to the input of said second counter, whereas said other processor is connected to the other input of said first counter and to the input of said third counter in such a manner that said reversible first counter is stepped in one direction and said second counter is stepped each time a said transmission is performed in one direction from said one to said other processor, whereas said reversible first counter is stepped in the other direction and said third counter is stepped each time a said transmission is performed in the other direction from said other to said one processor, when said second or third counter has counted said predetermined second value all said counters reset, and when said first reversible counter has counted said predetermined first value in one direction, an error indicating bistate device is set in said one processor in order to indicate that said other processor is faulty, whereas when said reversible second counter has counted said first predetermined value in said other direction another error indicating bistate device is set in said other processor in order to indicate that said one processor is faulty.

Claim 17

Automatic telecommunication switching system according to claim 15 in which said transmission means include two channels for transmitting said information between said pair of processors, said channels being unidirectional and comprising a first and a second said interprocessor register respectively, and one of said channels is connected to said one input of said first counter and to said input of said second counter, whereas the other channel is connected to said other input of said first counter and to said input of said third counter.

Claim 18

Automatic telecommunication switching system according to claim 1 wherein said memory means include a stored base level program, a stored clock interrupt program, and a stored interprocessor interrupt program; and wherein said system further includes a clock interrupt source and a plurality of interprocessor interrupt sources, said clock interrupt source when operated being able to temporarily interrupt said base level program and to start said clock interrupt program, whereas said interprocessor interrupt sources when operated are able to temporarily interrupt said base level program or said clock interrupt program and to start said interprocessor interrupt program during which said information is transmitted to at least one of the other processors by said transmission means.

Claim 19

Automatic telecommunication switching system according to claim 17 in which said base level program includes a maintenance subprogram, and said memory means further includes a stored asynchronous switching interrupt program, and in which said system includes a plurality of asynchronous switching interrupt sources which when operated are able to temporarily interrupt said base level program and to start said asynchronous switching interrupt program.

Claim 20

Automatic telecommunication switching system according to claim 18 wherein said base level program is adapted to control operations within the processor and the switching network, said clock interrupt program is adapted to control synchronous operations involving the processor and said switching network, said asynchronous switching interrupt program is adapted to control asynchronous operations involving the processor and said switching network, and said interprocessor interrupt program is adapted to control operations involving the processor and another processor.

Claim 21

Automatic telecommunication switching system according to claim 17 in which said interprocessor interrupt program of each processor comprises an interprocessor output interrupt program and an interprocessor input interrupt program, said plurality of interprocessor interrupt sources of each processor comprise an interprocessor output interrupt source and an interprocessor input interrupt source, and when an interprocessor output interrupt source is operated in a processor said interprocessor output interrupt pRogram is executed causing said transmission means to transmit said information from this processor to said first interprocessor register, whereas when said interprocessor input interrupt program is executed in a processor said interprocessor input interrupt program is executed causing said transmission means to transmit said information to this processor from said second interprocessor register.

Claim 22

Automatic telecommunication switching system according to claim 20 in which said memory means of each of said processors further include a first memory circuit for temporarily storing said information to be transferred to said first interprocessor register and a second memory circuit for temporarily storing said information received from said second interprocessor register, said interprocessor output interrupt source is operated when simultaneously said first memory circuit contains information, said first interprocessor register is idle and no program of higher priority is effective in said one processor, and said interprocessor input interrupt source is operated when simultaneously said second interprocessor register contains information, said second memory circuit is idle and no program of higher priority is effective in said one processor.

Claim 23

Automatic telecommunication switching system according to claim 17 in which a fault detection subprogram is included in said base level program and is adapted to check the condition of this processor and to inform the other processor when the processor is faulty by setting an error indicating means in the other processor, and said fault detection subprogram is also adapted to check the condition of said error indicating means included in this processor, the detection of an error indicating means in its set condition resulting in the start of a takeover program forming part of said base level program and by means of which said takeover operation is performed.

Claim 24

Automatic telecommunication switching system according to claim 17 wherein the clock interrupt programs of said two processors start at moments which are shifted with respect to one another so that these programs are prevented from simultaneously controlling the same elements in said switching network; and said clock interrupt programs comprise sequences of operations which are executed substantially in the same predetermined order in both said processors.

Claim 25

Automatic telecommunication switching system according to claim 18 wherein said asynchronous switching interrupt program of each processor comprises a first asynchronous switching interrupt subprogram controlling the transmission of information including orders and concerning communication control operations from said processor to said switching network and a second asynchronous switching interrupt subprogram controlling the transmission of information and also concerning communication control operations from said switching network to said processor; and wherein said switching network includes switching means and a plurality of network control means which have access to the whole of said switching means and which are each permanently connected via a single second transmission means to a distinct one of said processors and that said first and second asynchronous switching interrupt subprograms of a processor control the transmission of information from said processor to the associated network control means and vice versa via said second transmission means in order that said network control means and said processor respectively should process the information received.

Claim 26

Automatic telecommunication switching system according to claim 24 in which said switching means are constituted by a plurality of network parts, whereas each said network control means is constituted by a plurality of identical network control circuits and two network control circuits, each belonging to a distinct one of said network control means, are associated in a module to a said network part and are connected to distinct ones of said proceSsors by said second transmission means.

Claim 27

Automatic telecommunication switching system according to claim 25 in which each of the two network control circuits of a module includes an asynchronous switching control circuit which comprises a first and a second auxiliary asynchronous switching interrupt source, said first auxiliary asynchronous switching interrupt source when operated requests for the execution of a said first asynchronous switching interrupt subprogram controlling the transmission of information from the processor, associated to this network control circuit, to this asynchronous switching control circuit, said asynchronous switching control circuit is adapted to execute operations in the associated network part upon receipt of said information, and said second auxiliary asynchronous switching interrupt source when operated requests for the execution of a said second asynchronous switching interrupt subprogram controlling the transmission of information from this asynchronous switching control circuit to the associated processor.

Claim 28

Automatic telecommunication switching system according to claim 26 in which a said first auxiliary asynchronous switching interrupt source included in a module and associated to a processor may only be operated when information must be transmitted to the associated asynchronous switching control circuit, when both the asynchronous switching control circuits of the module are free and during the second half period of each time interval elapsing between the starts of two successive clock interrupt programs in said processor; and in which a said second auxiliary asynchronous switching interrupt source included in a module and associated to a processor may be operated when information must be transmitted to said processor after the execution of an operation.

Claim 29

Automatic telecommunication switching system according to claim 27 in which the outputs of the first and second auxiliary asynchronous switching interrupt sources associated to an asynchronous switching control circuit are connected to the first and second inputs of a first mixer the output of which is activated when this asynchronous switching control circuit requests for the execution of a first or a second asynchronous switching interrupt subprogram, the outputs of the first mixers associated to the various asynchronous switching control circuits associated to a same processor are connected to a second mixer the output of which constitutes the one input of a coincidence gate the other input of which is activated when no interrupt program of higher priority than the asynchronous switching interrupt program is taking place in said same processor, and when activated the output of said gate which constitutes said asynchronous switching interrupt source delivers an asynchronous switching interrupt signal which starts an asynchronous switching interrupt subprogram which consists in the scanning of the first and second inputs of said first mixer, in the selection of an activated one of these inputs and in the continuation of said first or of said second asynchronous switching interrupt subprogram in the associated asynchronous switching control circuit depending on the selected input being connected to a first or to a second auxiliary asynchronous switching interrupt source.

Claim 30

Automatic telecommunication switching system according to claim 28 wherein each said communication control operation performed in said switching network by a said processor consists in the control of a call connection between calling and called stations through a junctor and other switching means of said switching network, and said information transmitted from a said processor to an associated asynchronous switching control circuit by first asynchronous switching control interrupt subprograms may include orders to connect a junctor to the calling station, to connect feeding bridge and send dial tone to said calling station, to connect a junctor to the called station, to send continuous ringing tonE and current to calling and called stations, to stop immediate ringing and send interrupt ringing, and to release connection.

Claim 31

Automatic telecommunication switching system according to claim 17 wherein said base level program comprises a plurality of subprograms which are executed at a rhythm which is a submultiple of the rhythm at which said clock interrupt programs are executed, a counter is associated to each of said base level subprograms and is stepped each time a said clock interrupt program is executed, and said base level program comprises means for examining each of said counters of said subprograms, means for executing each said subprogram when the corresponding counter has counted a predetermined value and means for resetting this counter when this subprogram is finished.

Claim 32

Automatic telecommunication switching system according to claim 30 wherein each said communication control operation performed in said switching network by said processor consists in the control of a call connection between calling and called stations through a junctor and other switching means of said switching network which includes registers, each said clock interrupt program comprises means for scanning a loop between a calling station and a junctor at a first rhythm higher than that of the loop openings and closures produced by dialing the identity of a called station and bringing a time counter bit of a register in a predetermined first condition each time a said loop opening or closure is detected, and said base level program comprises means for examining the time counter bit of said register at a second rhythm lower than that of said loop openings and closures and bringing said time counter bit in a predetermined second condition, the fact that said time counter bit is found still to be in its second condition during a said base level program indicating that a loop opening or closure at least equal to the time interval between two successive examinations of the time counter bit of said register is being detected.

Claim 33

Automatic telecommunication switching system according to claim 17 wherein a said communication control operation performed in said switching network by said processor consists in the control of a call connection between calling and called stations through said switching network which includes registers and auxiliary registers, the identity of a called station being stored in a said register and after the storage of said identity ringing is sent to said called station and a said auxiliary register including a time counter is seized, whereas said register is released and said base level program includes a subprogram which is executed at a predetermined rhythm and which causes examination of the time counter of each auxiliary register seized and in the stepping of this counter by one step unless this counter is found in a predetermined position in which case the sending of said ringing is stopped.

Claim 34

Automatic telecommunication switching system according to claim 17 in which a said communication control operation performed in said switching network by said processors consists in the control of a call connection between calling and called stations through a junctor and other switching means of said switching network which includes supervision registers and when a call connection is released in one of the stations a said supervision register having a time counter is seized and said base level program further includes a subprogram which is executed at a predetermined rhythm and which causes the examination of each supervision register seized and in the stepping of this counter by one step unless this counter is found in a predetermined position in which case said call connection is released by releasing the junctor involved in this connection.

Claim 35

Automatic telecommunication switching system comprising a switching network and a programmed control system for said switching network, said control system including at least two programmed processors which simultaneously and Actively control the whole of said network, and said switching network includes switching means and a plurality of network control means which have access to the whole of said switching means and which are each permanently connected by a single transmission means to a distinct one of said processors; and said switching means are constituted by a plurality of network parts, whereas each said network control means is constituted by a plurality of identical network control circuits and two network control circuits, each belonging to a distinct one of said network control means, are associated in a module to a said network part and are connected to distinct ones of said processors by said second transmission means.

Claim 36

Automatic telecommunication switching system comprising a switching network and a programmed control system for said switching network, said control system including at least two programmed processors which simultaneously and Actively control the whole of said network, and said switching network includes switching means and a plurality of network control means which have access to the whole of said switching means and which are each permanently connected by a single transmission means to a distinct one of said processors; and said switching means are constituted by a plurality of network parts, whereas each said network control means is constituted by a plurality of identical network control circuits and two network control circuits, each belonging to a distinct one of said network control means, are associated in a module to a said network part and are connected to distinct ones of said processors by said second transmission means.

Claim 37

In an automatic telecommunication switching system including a plurality of stations, calling and called ones of which may be interconnected by junctors and other switching means, and registers, the system comprising first means to scan a loop between a calling station and a junctor at a rhythm higher than that of the loop openings and closures produced by dialing the identity of a called station and to bring a time counter bit of a said register in a predetermined first condition each time a said loop opening or closure is detected, and second means to examine the time counter bit of said register at a rhythm lower than that of said loop openings and closures and bringing said time counter bit in a predetermined second condition if it had previously been brought in said first condition by said first means, said time counter bit being found in its second condition by said second means indicates that a loop closure or opening having a duration at least equal to the time interval between two successive examinations of the time counter bit of said register is being detected.

Claim 38

In an automatic telecommunication switching system including a plurality of stations, calling and called ones of which may be interconnected by junctors and other switching means, and registers, the system comprising first means to scan a loop between a calling station and a junctor at a rhythm higher than that of the loop openings and closures produced by dialing the identity of a called station and to bring a time counter bit of a said register in a predetermined first condition each time a said loop opening or closure is detected, and second means to examine the time counter bit of said register at a rhythm lower than that of said loop openings and closures and bringing said time counter bit in a predetermined second condition if it had previously been brought in said first condition by said first means, said time counter bit being found in its second condition by said second means indicates that a loop closure or opening having a duration at least equal to the time interval between two successive examinations of the time counter bit of said register is being detected.

Claim 39

An information handling system including: at least two programmed processors which are able to simultaneously and actively perform distinct control operations; transmission means for transmitting information concerning said control operations performed by each one of said processors to at least one of the other processors; memory means in each one of said processors having stored therein a base level program, a clock interrupt program, and an interprocessor interrupt program; and said system further includes a clock interrupt source and interprocessor interrupt sources, said clock interrupt source when operated being able to temporarily interrupt said base level program and to start said clock interrupt program, whereas said interprocessor interrupt sources when operated are able to temporarily interrupt said base level program or said clock interrupt program and to start said interprocessor interrupt program during which said information is transmitted to at least one of the other processors by said transmission means.

Claim 40

An information handling system including: at least two programmed processors which are able to simultaneously and actively perform distinct control operations; transmission means for transmitting information concerning said control operations performed by each one of said processors to at least one of the other processors; memory means in each one of said processors having stored therein a base level program, a clock interrupt program, and an interprocessor interrupt program; and said system further includes a clock interrupt source and interprocessor interrupt sources, said clock interrupt source when operated being able to temporarily interrupt said base level program and to start said clock interrupt program, whereas said interprocessor interrupt sources when operated are able to temporarily interrupt said base level program or said clock interrupt program and to start said interprocessor interrupt program during which said information is transmitted to at least one of the other processors by said transmission means.