US3720819A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Direct digital computer control error detector system
Assignee: ExxonMobil Technology and Engineering Co
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Filing: 1971-11-26
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Granted: 1973-03-13
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Expires: 1991-11-26
Abstract
Abstract An error detection device for a direct digital process control computer detects at least two common computer output errors and immediately informs the computer and the operator of such error. The two types of errors are (a) a difference between two digitalto-analogue converter (DAC) outputs that is larger than a predetermined limit, and (2) two or more bits in an ECO word at the same time. Preferably it also detects (3) a DAC output that is less than a predetermined limit, and (4) a DAC output that is greater than a predetermined limit. On detecting an error, the device sends a process interrupt signal to the computer, switches the affected controller to backup controls, and operates an alarm to alert the operator.
Inventors
- 👤 C Newton
- 👤 E Harrison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:35
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1608; G06F11/08; G06F11/085
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
505 words
A system for the detection of erroneous control information produced in a digital computer operating a direct digital control system, which comprises: A direct digital control computer for generating digital control signals responsive to selected conditions in a controlled process and for generating at least two multiple-bit ECO words capable of identifying a controlled device, each of said words containing at least three bits, a first digital-to-analog converter operative to convert a digital control signal into a corresponding first output control voltage for controlling one of a plurality of controllers, a second digital-to-analog converter operative to convert said digital control signal into a corresponding second output control voltage which is normally the same as the first output control voltage, a differential voltage comparator-amplifier responsive to said first output control voltage and said second output control voltage and operative to generate a first error signal when the voltage differential between the first output control voltage and the second output control voltage exceeds a preset maximum, and containing a time delay circuit for said first output control voltage, a first latch circuit responsive to the first error signal from said differential voltage comparator-amplifier to generate a first process interrupt voltage and a first backup control activate signal, amplifying means responsive to the first backup control activate signal and operative to engage backup control means operatively associated with said controllers to operate said controllers, for each identifying word, a plurality of ECO checking circuits equal in number to the number of bits in said word, each of ECO checking circuits comprising: an OR gate responsive to all but one of the bits of said word and operative to generate an ON state signal, which may be binary 1 or binary 0, if any of the input bits is the same ON state binary digit, an AND gate responsive to the one bit of said word to which the OR gate is nonresponsive and to the output from said OR gate to generate an alarm signal if both the one bit and the OR gate output are the same ON state binary digit, an ECO alarm latching circuit responsive to an alarm signal from said AND gate and operative to generate a second process interrupt voltage and a second backup control activate signal, amplifying means responsive to said second backup control activate signal and operative to engage backup control means operatively associated with said controllers to operate said controllers, each of said ECO checking circuits receiving a different one of said bits of said word as an input to an AND gate, a plurality of control circuits each having a plurality of switches with one switch for each of said words, each switch being responsive to only one bit of only one of said words, such that said first output control voltage will be transmitted to a particular controller only if said one bit of each of said words is received from said digital computer, and a plurality of controllers each responsive to only one of said control circuits.
Claim 2
Independent Claim
505 words
A system for the detection of erroneous control information produced in a digital computer operating a direct digital control system, which comprises: A direct digital control computer for generating digital control signals responsive to selected conditions in a controlled process and for generating at least two multiple-bit ECO words capable of identifying a controlled device, each of said words containing at least three bits, a first digital-to-analog converter operative to convert a digital control signal into a corresponding first output control voltage for controlling one of a plurality of controllers, a second digital-to-analog converter operative to convert said digital control signal into a corresponding second output control voltage which is normally the same as the first output control voltage, a differential voltage comparator-amplifier responsive to said first output control voltage and said second output control voltage and operative to generate a first error signal when the voltage differential between the first output control voltage and the second output control voltage exceeds a preset maximum, and containing a time delay circuit for said first output control voltage, a first latch circuit responsive to the first error signal from said differential voltage comparator-amplifier to generate a first process interrupt voltage and a first backup control activate signal, amplifying means responsive to the first backup control activate signal and operative to engage backup control means operatively associated with said controllers to operate said controllers, for each identifying word, a plurality of ECO checking circuits equal in number to the number of bits in said word, each of ECO checking circuits comprising: an OR gate responsive to all but one of the bits of said word and operative to generate an ON state signal, which may be binary 1 or binary 0, if any of the input bits is the same ON state binary digit, an AND gate responsive to the one bit of said word to which the OR gate is nonresponsive and to the output from said OR gate to generate an alarm signal if both the one bit and the OR gate output are the same ON state binary digit, an ECO alarm latching circuit responsive to an alarm signal from said AND gate and operative to generate a second process interrupt voltage and a second backup control activate signal, amplifying means responsive to said second backup control activate signal and operative to engage backup control means operatively associated with said controllers to operate said controllers, each of said ECO checking circuits receiving a different one of said bits of said word as an input to an AND gate, a plurality of control circuits each having a plurality of switches with one switch for each of said words, each switch being responsive to only one bit of only one of said words, such that said first output control voltage will be transmitted to a particular controller only if said one bit of each of said words is received from said digital computer, and a plurality of controllers each responsive to only one of said control circuits.
Claim 3
Independent Claim
505 words
A system for the detection of erroneous control information produced in a digital computer operating a direct digital control system, which comprises: A direct digital control computer for generating digital control signals responsive to selected conditions in a controlled process and for generating at least two multiple-bit ECO words capable of identifying a controlled device, each of said words containing at least three bits, a first digital-to-analog converter operative to convert a digital control signal into a corresponding first output control voltage for controlling one of a plurality of controllers, a second digital-to-analog converter operative to convert said digital control signal into a corresponding second output control voltage which is normally the same as the first output control voltage, a differential voltage comparator-amplifier responsive to said first output control voltage and said second output control voltage and operative to generate a first error signal when the voltage differential between the first output control voltage and the second output control voltage exceeds a preset maximum, and containing a time delay circuit for said first output control voltage, a first latch circuit responsive to the first error signal from said differential voltage comparator-amplifier to generate a first process interrupt voltage and a first backup control activate signal, amplifying means responsive to the first backup control activate signal and operative to engage backup control means operatively associated with said controllers to operate said controllers, for each identifying word, a plurality of ECO checking circuits equal in number to the number of bits in said word, each of ECO checking circuits comprising: an OR gate responsive to all but one of the bits of said word and operative to generate an ON state signal, which may be binary 1 or binary 0, if any of the input bits is the same ON state binary digit, an AND gate responsive to the one bit of said word to which the OR gate is nonresponsive and to the output from said OR gate to generate an alarm signal if both the one bit and the OR gate output are the same ON state binary digit, an ECO alarm latching circuit responsive to an alarm signal from said AND gate and operative to generate a second process interrupt voltage and a second backup control activate signal, amplifying means responsive to said second backup control activate signal and operative to engage backup control means operatively associated with said controllers to operate said controllers, each of said ECO checking circuits receiving a different one of said bits of said word as an input to an AND gate, a plurality of control circuits each having a plurality of switches with one switch for each of said words, each switch being responsive to only one bit of only one of said words, such that said first output control voltage will be transmitted to a particular controller only if said one bit of each of said words is received from said digital computer, and a plurality of controllers each responsive to only one of said control circuits.
Claim 4
Independent Claim
505 words
A system for the detection of erroneous control information produced in a digital computer operating a direct digital control system, which comprises: A direct digital control computer for generating digital control signals responsive to selected conditions in a controlled process and for generating at least two multiple-bit ECO words capable of identifying a controlled device, each of said words containing at least three bits, a first digital-to-analog converter operative to convert a digital control signal into a corresponding first output control voltage for controlling one of a plurality of controllers, a second digital-to-analog converter operative to convert said digital control signal into a corresponding second output control voltage which is normally the same as the first output control voltage, a differential voltage comparator-amplifier responsive to said first output control voltage and said second output control voltage and operative to generate a first error signal when the voltage differential between the first output control voltage and the second output control voltage exceeds a preset maximum, and containing a time delay circuit for said first output control voltage, a first latch circuit responsive to the first error signal from said differential voltage comparator-amplifier to generate a first process interrupt voltage and a first backup control activate signal, amplifying means responsive to the first backup control activate signal and operative to engage backup control means operatively associated with said controllers to operate said controllers, for each identifying word, a plurality of ECO checking circuits equal in number to the number of bits in said word, each of ECO checking circuits comprising: an OR gate responsive to all but one of the bits of said word and operative to generate an ON state signal, which may be binary 1 or binary 0, if any of the input bits is the same ON state binary digit, an AND gate responsive to the one bit of said word to which the OR gate is nonresponsive and to the output from said OR gate to generate an alarm signal if both the one bit and the OR gate output are the same ON state binary digit, an ECO alarm latching circuit responsive to an alarm signal from said AND gate and operative to generate a second process interrupt voltage and a second backup control activate signal, amplifying means responsive to said second backup control activate signal and operative to engage backup control means operatively associated with said controllers to operate said controllers, each of said ECO checking circuits receiving a different one of said bits of said word as an input to an AND gate, a plurality of control circuits each having a plurality of switches with one switch for each of said words, each switch being responsive to only one bit of only one of said words, such that said first output control voltage will be transmitted to a particular controller only if said one bit of each of said words is received from said digital computer, and a plurality of controllers each responsive to only one of said control circuits.
Claim 5
Dependent Claim
99 words
The system of claim 1 further comprising: a low voltage comparator-amplifier responsive to said first output control voltage and a preset minimum voltage standard and operative to generate a second error signal when said first output control voltage falls below said preset minimum voltage standard, and containing a time delay circuit for said first output control voltage, a second latch circuit responsive to said second error signal from said low voltage comparator-amplifier to generate a second process interrupt signal and a second backup control activate signal, said amplifying means further being responsive to said second backup control activate signal.
Claim 6
Dependent Claim
97 words
The system of claim 1 further comprising: a high voltage comparator-amplifier responsive to said first output control voltage and a preset maximum voltage standard and operative to generate a third error signal when said first output control voltage exceeds said maximum voltage standard, and containing a time delay circuit for said first output control voltage, a third latch circuit responsive to said third error signal from said high voltage comparator-amplifier to generate a third process interrupt signal and a third backup control activate signal, said amplifying means further being responsive to said third backup control activate signal.
Claim 7
Dependent Claim
21 words
A system in accordance with claim 1 in which the time delay circuit in said differential voltage comparator-amplifier is 200 microseconds.
Claim 8
Dependent Claim
506 words
An error detection system for detecting erroneous control information from a direct digital control computer linked to a plurality of process controllers in a process control system, wherein: said computer generates digital control signals in response to selected conditions in a controlled process, and a first digital-to-analog converter converts such a control signal into a first output control voltage, said computer also generating at least two multiple bit ECO words of at least three bits each for identifying the particular controller to receive said first output voltage, and wherein said process controllers each have a control circuit containing a plurality of switches with one switch for each of said words, each switch being responsive to only one bit of only one of said words such that said first output control voltage will be transmitted to a particular controller only if said one bit of each of said words is received from said digital computer, and wherein each of said controllers is operatively associated with backup control means for operating such controller on interruption of direct control from said computer, said system comprising: a second digital-to-analog converter operative to convert said digital control signal into a corresponding second output control voltage which is normally the same as the first output control voltage, a differential voltage comparator-amplifier responsive to said first output control voltage and said second output control voltage aNd operative to generate a first error signal when the voltage differential between the first output control voltage and the second output control voltage exceed a preset maximum, and containing a time delay circuit for said first output control voltage, a first latch circuit responsive to the first error signal from said differential voltage comparator-amplifier to generate a first process interrupt signal and a first backup control activate signal, amplifying means responsive to the first backup control activate signal and operative to engage said backup control means; and for each identifying word, a plurality of ECO checking circuits equal in number to the number of bits in said word, each of said ECO checking circuits comprising: an OR gate responsive to all but one of the bits of said word and operative to generate an ON state signal, which may be binary 1 or binary 0, if any of the input bits is the same ON state binary digit, an AND gate responsive to the one bit of said word to which the OR gate is nonresponsive and to the output from said OR gate to generate an alarm signal if both the one bit and the OR gate output are the same ON state binary digit, an ECO alarm latching circuit responsive to an alarm signal from said AND gate and operative to generate a second process interrupt signal and a second backup control activate signal, amplifying means responsive to said second backup control activate signal and operative to engage said backup control means, each of said ECO checking circuits receiving a different one of said bits of said word as an input to an AND gate.
Claim 9
Dependent Claim
506 words
An error detection system for detecting erroneous control information from a direct digital control computer linked to a plurality of process controllers in a process control system, wherein: said computer generates digital control signals in response to selected conditions in a controlled process, and a first digital-to-analog converter converts such a control signal into a first output control voltage, said computer also generating at least two multiple bit ECO words of at least three bits each for identifying the particular controller to receive said first output voltage, and wherein said process controllers each have a control circuit containing a plurality of switches with one switch for each of said words, each switch being responsive to only one bit of only one of said words such that said first output control voltage will be transmitted to a particular controller only if said one bit of each of said words is received from said digital computer, and wherein each of said controllers is operatively associated with backup control means for operating such controller on interruption of direct control from said computer, said system comprising: a second digital-to-analog converter operative to convert said digital control signal into a corresponding second output control voltage which is normally the same as the first output control voltage, a differential voltage comparator-amplifier responsive to said first output control voltage and said second output control voltage aNd operative to generate a first error signal when the voltage differential between the first output control voltage and the second output control voltage exceed a preset maximum, and containing a time delay circuit for said first output control voltage, a first latch circuit responsive to the first error signal from said differential voltage comparator-amplifier to generate a first process interrupt signal and a first backup control activate signal, amplifying means responsive to the first backup control activate signal and operative to engage said backup control means; and for each identifying word, a plurality of ECO checking circuits equal in number to the number of bits in said word, each of said ECO checking circuits comprising: an OR gate responsive to all but one of the bits of said word and operative to generate an ON state signal, which may be binary 1 or binary 0, if any of the input bits is the same ON state binary digit, an AND gate responsive to the one bit of said word to which the OR gate is nonresponsive and to the output from said OR gate to generate an alarm signal if both the one bit and the OR gate output are the same ON state binary digit, an ECO alarm latching circuit responsive to an alarm signal from said AND gate and operative to generate a second process interrupt signal and a second backup control activate signal, amplifying means responsive to said second backup control activate signal and operative to engage said backup control means, each of said ECO checking circuits receiving a different one of said bits of said word as an input to an AND gate.
Claim 10
Dependent Claim
93 words
The system of claim 5 further comprising: a low voltage comparator-amplifier responsive to said first output control voltage and a preset minimum voltage standard and operative to generate a second error signal when said first output control voltage falls below said preset minimum voltage standard, and containing a time delay circuit for said first output control voltage, a second latch circuit responsive to said second error signal from said low voltage comparator-amplifier to generate a second backup control activate signal, said amplifying means further being responsive to said second backup control activate signal.
Claim 11
Dependent Claim
97 words
The system of claim 5 further comprising: a high voltage comparator-amplifier responsive to said first output control voltage and a preset maximum voltage standard and operative to generate a third error signal when said first output control voltage exceeds said maximum voltage standard, and containing a time delay circuit for said first output control voltage, a third latch circuit responsive to said third error signal from said high voltage comparator-amplifier to generate a third process interrupt signal and a third backup control activate signal, said amplifying means further being responsive to said third backup control activate signal.
Claim 12
Dependent Claim
21 words
A system in accordance with claim 5 in which the time delay circuit in said differential voltage comparator-amplifier is 200 microseconds.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-12 | 1976-09-11 | 1977-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-12 | 1980-09-11 | 1981-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-12 | 1984-09-11 | 1985-03-13 | $7700.00 | Window Closed / Lapsed |