US3618015A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for discriminating between errors and faults
Assignee: AG Communication Systems Corp
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Filing: 1970-06-30
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Granted: 1971-11-02
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Expires: 1990-06-30
Abstract
Abstract Signal points of duplicated subsystems are compared, to produce a mismatch if they differ. Since mismatches due to errors caused by noise, etc. occur infrequently and at random, and are of short duration, relative to mismatches caused by actual faults; apparatus to discriminate between them comprises a high frequency of occurrence of mismatches unit, and an extended mismatch unit. The high frequency of occurrence unit includes a counter and timer to detect whether a given number of mismatches occur within a given time. The extended mismatch unit may comprise a capacitor connected to standard logic devices to charge during a mismatch via resistance within the logic devices, and to be shortcircuited via a transistor in a logic device at other times.
Inventors
- 👤 Henry Peter Homonick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:34
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/16; G06F11/1608
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
244 words
In combination, comparison means connected to compare logic signal conditions at corresponding points of two subsystems and to produce a given signal condition on a mismatch conductor at an output of the comparison means responsive to a noncomparison at any corresponding points of the two subsystems; ''''frequency-of-mismatch'''' means comprising a counter and a first timer, means responsive to each occurrence of said given signal condition on the mismatch conductor to advance the counter, means responsive to a nonzero output from the counter to actuate the first timer, means responsive to the first timer being continuously actuated for a first time interval to reset the counter to zero, and means responsive to the counter reaching a given count while the first timer is actuated for less than the first time interval to produce a signal on a ''''high-frequency-of-mismatch'''' output conductor; ''''extended-mismatch'''' means comprising a second timer, means responsive to said given signal condition on the mismatch conductor to actuate the second timer, means responsive to absence of the given signal condition on the mismatch conductor to reset the second timer, and means responsive to the second timer being continuously actuated for a second time interval to produce a signal on an ''''extended-mismatch'''' output conductor; and OR gating means having the ''''high-frequency-of-mismatch'''' and ''''extended-mismatch'''' conductors connected to inputs thereof, so that a signal appearing at an output thereof responsive to a signal on either of the inputs indicates a probable fault in one of said subsystems.
Claim 2
Dependent Claim
244 words
In combination, comparison means connected to compare logic signal conditions at corresponding points of two subsystems and to produce a given signal condition on a mismatch conductor at an output of the comparison means responsive to a noncomparison at any corresponding points of the two subsystems; ''''frequency-of-mismatch'''' means comprising a counter and a first timer, means responsive to each occurrence of said given signal condition on the mismatch conductor to advance the counter, means responsive to a nonzero output from the counter to actuate the first timer, means responsive to the first timer being continuously actuated for a first time interval to reset the counter to zero, and means responsive to the counter reaching a given count while the first timer is actuated for less than the first time interval to produce a signal on a ''''high-frequency-of-mismatch'''' output conductor; ''''extended-mismatch'''' means comprising a second timer, means responsive to said given signal condition on the mismatch conductor to actuate the second timer, means responsive to absence of the given signal condition on the mismatch conductor to reset the second timer, and means responsive to the second timer being continuously actuated for a second time interval to produce a signal on an ''''extended-mismatch'''' output conductor; and OR gating means having the ''''high-frequency-of-mismatch'''' and ''''extended-mismatch'''' conductors connected to inputs thereof, so that a signal appearing at an output thereof responsive to a signal on either of the inputs indicates a probable fault in one of said subsystems.
Claim 3
Dependent Claim
83 words
The combination as claimed in claim 1, wherein said second timer comprises a capacitor connected to a timer conductor between digital logic devices containing resistive biasing circuit means, with the logic devices including means coupled to the mismatch conductor and to the timer conductor to cause the capacitor to charge via said resistive means responsive to said given signal condition on the mismatch conductor, and to cause the capacitor to be short circuit shunted responsive to the absence of the given signal condition.
Claim 4
Dependent Claim
89 words
The combination as claimed in claim 2, wherein said logic devices include an input bistable device coupled between the mismatch conductor and the capacitor; the bistable device having a ''''set'''' state and the a ''''reset'''' state, with means to actuate it to the ''''set'''' state responsive to the given signal condition and to actuate it to the ''''reset'''' state responsive to absence of the given signal condition on the mismatch conductor; and the short circuit shunt path for the capacitor being via switching means within the first bistable device.
Claim 5
Dependent Claim
64 words
The combination as claimed in claim 3, Wherein said logic devices further include an output bistable device having input means coupled to said timing conductor, so that it is actuated to a ''''set'''' state responsive to said second time being actuated for said second time interval, and it is actuated to a ''''reset'''' state responsive to the ''''reset'''' state of said input bistable device.
Claim 6
Dependent Claim
69 words
The combination as claimed in claim 3, wherein said logic devices include an output device having an input connected to said timer conductor, and wherein said resistive biasing circuit means includes biasing resistance means internal to the output device connected between the input and voltage source means; all of said logic devices being standard module types; and wherein said capacitor may be changed to change said second time interval.
Claim 7
Dependent Claim
159 words
The combination as claimed in claim 3, wherein said logic devices include a pulse gating device having a pulse input, direct-coupled control input means, and an output, for producing a pulse at its output responsive to enabling signals at the control input means and the occurrence of a pulse at the pulse input; with the pulse input connected to a source of recurring clock pulses, and the control input means coupled to said mismatch conductor so that responsive to said given signal condition on the mismatch conductor a pulse is produced at the output for each clock pulse at the pulse input; the output of the pulse gating device being coupled to both the counter of said ''''frequency-of-mismatch means'''' and said input bistable device of the ''''extended-mismatch'''' means; the counter being advanced responsive to each pulse and the input bistable device being actuated to its ''''set'''' state responsive to the pulses from the output of the pulse gating device.
Claim 8
Dependent Claim
45 words
The combination as claimed in claim 6, wherein said input bistable device has an input direct-coupled to an output conductor from said comparison means having an inverted form of the signal on the mismatch conductor, thereby providing said means to actuate to its ''''reset'''' state.
Claim 9
Dependent Claim
123 words
The combination as claimed in claim 7, wherein said input bistable device is a flip-flop having set and reset input means, each with a pulse input and a direct-coupled control input, each input means being enabled by either an open circuit or one logic condition at the direct-coupled control input to respond to a pulse at the pulse input; the set input means having the pulse input connected to the output of said pulse gating means with the direct-coupled input an open circuit, and the reset input means having the pulse input connected to the source of clock pulses and the direct-coupled input connected to said output conductor from the comparison means having an inverted form of the signal on the mismatch conductor.
Claim 10
Dependent Claim
60 words
The combination as claimed in claim 7, wherein said logic devices include an output gate device which comprises at least part of said OR gating means, the gate device having an input connected to said timer conductor, and wherein said resistive biasing circuit means includes resistance means internal to the gate device connected between the input and voltage source means.
Claim 11
Dependent Claim
52 words
The combination as claimed in claim 9, wherein said direct-coupled input control means of the pulse gating device comprises a plurality of inputs, one of which is connected to an output of said input bistable device to inhibit the pulse gating device when the input bistable device is in its ''''set'''' state.
Claim 12
Dependent Claim
100 words
The combination as claimed in claim 10, wherein said logic devices further include an output bistable device having input means coupled to an output of said OR gating means, with means to actuate the output bistable device to a ''''set'''' state responsive to a signal from the OR gating means produced by either the ''''high-frequency-of-mismatch'''' or ''''extended-mismatch'''' conductors and to actuate it to a ''''reset'''' state in the absence of said signal from the OR gating means; an oUtput of the output bistable device being connected to a ''''valid mismatch'''' conductor on which a signal condition indicates a probable fault.
Claim 13
Dependent Claim
66 words
The combination as claimed in claim 11, wherein said first timer includes a ''''time out'''' bistable device which is actuated to a ''''set'''' state responsive to the timer being actuated for said first time interval; wherein the first timer includes an external resistor which may be changed to change said first time interval; and wherein said capacitor may be changed to change said second time interval.
Claim 14
Dependent Claim
73 words
The combination as claimed in claim 12, further including OR gate means having inputs from said ''''time out'''' bistable device and from said ''''valid mismatch'''' conductor and an output connected to said counter to provide said means to reset the counter to 0 and an inverted output of the last said OR gate means being connected to an input of said direct-coupled input control means of the pulse gating device to inhibit it.
Claim 15
Dependent Claim
32 words
The combination as claimed in claim 13, further including manual switch control means connected to several of said conductors and logic devices to simulate or inhibit various conditions for testing the circuits.
Claim 16
Dependent Claim
17 words
The combination as claimed in claim 13, wherein all of said logic devices are standard module types.
Claim 17
Dependent Claim
45 words
The combination as claimed in claim 13, further including gate means between said comparison means and the mismatch conductor, having input connections from said ''''time out'''' bistable device and from said ''''valid mismatch'''' conductor to inhibit producing said given signal condition on the mismatch conductor.
Claim 18
Dependent Claim
30 words
The combination as claimed in claim 16, further including manual switch control means connected to the last said gate means to inhibit producing said given condition on the mismatch conductor.
Claim 19
Dependent Claim
26 words
The combination as claimed in claim 13, wherein said comparison means comprises a plurality of comparators, and gate means between each comparator and the mismatch conductor.
Claim 20
Dependent Claim
34 words
The combination as claimed in claim 18, further including manual switch means connected to the gate means following each comparator, to selectively inhibit each from producing said given signal condition on the mismatch conductor.
Claim 21
Dependent Claim
40 words
The combination as claimed in claim 19, wherein said gate means following the comparators have input connections from said ''''time out'''' bistable device and from said ''''valid mismatch'''' conductor to inhibit producing said given signal condition on the mismatch conductor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-01 | 1975-05-03 | 1975-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-01 | 1979-05-03 | 1979-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-01 | 1983-05-03 | 1983-11-02 | $7700.00 | Window Closed / Lapsed |