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US5976899A Expired / Lapsed US ⏱️ 0.0 years remaining

Reduced terminal testing system

Assignee: Micron Technology Inc
•
Filing: 1997-10-10
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Granted: 1999-11-02
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Expires: 2017-10-10
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Abstract

Abstract A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.

Inventors

  • 👤 Warren M. Farnworth
  • 👤 Leland R. Nevill
  • 👤 Raymond J. Beffa
  • 👤 Eugene H. Cloud

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 11:54
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2868; G01R31/2832; G01R31/2836; G01R31/2839; G01R31/2841; G01R31/2856; G01R31/317; G01R31/31701; G01R31/3181; G01R31/3185; G01R31/318505; G01R31/318511; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/1201; G11C29/48; H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; G01R31/282; G01R31/2831

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 152 words
A method of manufacturing a wafer, the method comprising the steps of: providing a substrate; forming a plurality of dice on the substrate, at least one die of the plurality of dice including circuitry responsive to being placed into a mode when the circuitry receives an alternating signal having predetermined characteristics, the circuitry of the at least one die responsive to an alternating signal having predetermined characteristics applied simultaneously with a V cc signal to the circuitry; providing a probe pad on the substrate; and forming a conductive path between the probe pad on the substrate and at least one dice of the plurality of dice, the conductive path connecting the at least one die including circuitry to the probe pad on the substrate for the circuitry of the at least one die being responsive to an alternating signal having predetermined characteristics applied simultaneously with a V cc signal to the circuitry.
Claim 2
Independent Claim 152 words
A method of manufacturing a wafer, the method comprising the steps of: providing a substrate; forming a plurality of dice on the substrate, at least one die of the plurality of dice including circuitry responsive to being placed into a mode when the circuitry receives an alternating signal having predetermined characteristics, the circuitry of the at least one die responsive to an alternating signal having predetermined characteristics applied simultaneously with a V cc signal to the circuitry; providing a probe pad on the substrate; and forming a conductive path between the probe pad on the substrate and at least one dice of the plurality of dice, the conductive path connecting the at least one die including circuitry to the probe pad on the substrate for the circuitry of the at least one die being responsive to an alternating signal having predetermined characteristics applied simultaneously with a V cc signal to the circuitry.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-11-01 2003-05-03 2003-11-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-11-01 2007-05-03 2007-11-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-11-01 2011-05-03 2011-11-02 $7700.00 Window Closed / Lapsed

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