Patent US2266226A successfully refreshed from Google Patents.
US5034685A
Expired / Lapsed
US
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Test device for testing integrated circuits
Assignee: DRI TECHNOLOGY Corp A CORP OF CALIFORNIA
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Filing: 1989-11-14
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Granted: 1991-07-23
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Expires: 2009-11-14
Abstract
Abstract Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of CAD. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure. The tester surface traces are then connected, by means of multiplexers, to a conventional tester signal processor.
Inventors
- 👤 Glenn J. Leedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:42
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/0735; G01R31/00; G01R31/28; G01R31/282; G01R31/2831; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31912; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70466; G03F7/70483; G03F7/70605; G03F7/70653; G03F7/70658; G11; G11C; G11C29/00; G11C29/006; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
113 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a flexible tester surface having a thickness of no greater than 15 microns and having a number of probe points corresponding to said contact points of said wafer; means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; and means for supplying programmable input/output diagnostic signals to said flexible tester surface for testing the electrical devices and circuitry of said wafer.
Claim 2
Dependent Claim
113 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a flexible tester surface having a thickness of no greater than 15 microns and having a number of probe points corresponding to said contact points of said wafer; means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; and means for supplying programmable input/output diagnostic signals to said flexible tester surface for testing the electrical devices and circuitry of said wafer.
Claim 3
Dependent Claim
20 words
The test device of claim 1, wherein said flexible tester surface comprises at least one thin sheet of flexible material.
Claim 4
Dependent Claim
15 words
The test device of claim 2, wherein said thin sheet comprises low stress silicon dioxide.
Claim 5
Dependent Claim
27 words
The test device of claim 1, wherein said probe points have a size less than 5 mils on a side and less than 10 mils in height.
Claim 6
Dependent Claim
17 words
The test device of claim 1, wherein the number of probe points is at least one thousand.
Claim 7
Dependent Claim
20 words
The test device of claim 1, wherein the probe points each have a diameter of about 2 to 4 microns.
Claim 8
Dependent Claim
20 words
The test device of claim 1, wherein the probe points each have a diameter of about 2 to 4 mils.
Claim 9
Dependent Claim
29 words
The test device of claim 1, further comprising logic circuitry for providing said diagnostic signals to the probe points, said logic circuitry being formed on the flexible tester surface.
Claim 10
Dependent Claim
26 words
The test device of claim 1, wherein the probe points are located at both a central portion and a peripheral portion of said flexible tester surface.
Claim 11
Dependent Claim
23 words
The device of claim 1, wherein the probe points are capable of electrically contacting each transistor in a portion of the integrated circuit.
Claim 12
Dependent Claim
104 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a flexible tester surface having at least one thousand probe points corresponding to said contact points of said wafer; means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; and means for supplying programmable input/output diagnostic signals to said flexible tester surface for testing the electrical devices and circuitry of said wafer.
Claim 13
Dependent Claim
104 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a flexible tester surface having at least one thousand probe points corresponding to said contact points of said wafer; means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; and means for supplying programmable input/output diagnostic signals to said flexible tester surface for testing the electrical devices and circuitry of said wafer.
Claim 14
Dependent Claim
119 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a flexible tester surface, said flexible tester surface having a number of probe points corresponding to said contact points of said wafer, wherein each probe point has a diameter not greater than four microns; means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; and means for supplying programmable input/output diagnostic signals to said flexible tester surface for testing the electrical devices and circuitry of said wafer.
Claim 15
Dependent Claim
119 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a flexible tester surface, said flexible tester surface having a number of probe points corresponding to said contact points of said wafer, wherein each probe point has a diameter not greater than four microns; means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; and means for supplying programmable input/output diagnostic signals to said flexible tester surface for testing the electrical devices and circuitry of said wafer.
Claim 16
Dependent Claim
109 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a flexible tester surface having a number of probe points corresponding to said contact points of said wafer; means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; programmable input/output circuitry formed on the flexible tester surface for supplying diagnostic signals to each of said probe points for testing the electrical devices and circuitry of said wafer.
Claim 17
Dependent Claim
109 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a flexible tester surface having a number of probe points corresponding to said contact points of said wafer; means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; programmable input/output circuitry formed on the flexible tester surface for supplying diagnostic signals to each of said probe points for testing the electrical devices and circuitry of said wafer.
Claim 18
Dependent Claim
136 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a tester surface disposed on said support, said tester surface having a number of probe points corresponding to said contact points of said wafer; means for electrically interconnecting said probe points of said tester means and said contact points of said wafer; means for supplying programmable input/output diagnostic signals to said tester surface for testing the electrical devices and circuitry of said wafer; and interconnect circuitry formed on the tester surface for connecting the means for supplying to said probe points and including at least two conductive layers separated by an insulating layer.
Claim 19
Dependent Claim
136 words
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising: a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon; a tester surface disposed on said support, said tester surface having a number of probe points corresponding to said contact points of said wafer; means for electrically interconnecting said probe points of said tester means and said contact points of said wafer; means for supplying programmable input/output diagnostic signals to said tester surface for testing the electrical devices and circuitry of said wafer; and interconnect circuitry formed on the tester surface for connecting the means for supplying to said probe points and including at least two conductive layers separated by an insulating layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-22 | 1995-01-21 | 1995-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-22 | 1999-01-21 | 1999-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-22 | 2003-01-21 | 2003-07-23 | $7700.00 | Window Closed / Lapsed |