Patent US747108A successfully refreshed from Google Patents.
US5872797A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Burn-in signal pattern generator
Assignee: International Business Machines Corp
•
Filing: 1996-12-02
•
Granted: 1999-02-16
•
Expires: 2016-12-02
Abstract
Abstract Hardware tester and burn-in tools are emulated by providing a user-specified nested sequence of counters, logical combination of the counter outputs and generation of corresponding vectors for application to exercise an integrated circuit device. The vectors are generated in accordance with user-specified parameters and stored in static random access memory until called for application to the integrated circuit. The parameters, preferably specified through use of a graphic user interface, provide an extremely compressed representation of the vectors themselves. Provision is made to accommodate any of a plurality of waveform conventions directly in the vector. An interface table is preferably used to arbitrarily allocate bits of the vector to pins of the integrated circuit device and any of a plurality of clock signals and phases can be provided to any pin. Sequences of vectors may also be generated for each combination of counter output states in accordance with desired memory functions.
Inventors
- 👤 Philip Theodoseau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:47
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
124 words
A system for exercising integrated circuits, comprising: a plurality of counters, means for specifying a counting function of each of said plurality of counters, means for providing ordered nesting of counting of said plurality of counters, means for simultaneously storing a plurality of macros, each of said macros combining outputs of said plurality of counters in a predetermined manner, means for selecting one of said plurality of macros, means for forming logic signals from the outputs of said plurality of counters in accordance with said selected macro, means for specifying a waveform convention in accordance with each of said logic signals, and means for outputting a vector as an input to an integrated circuit in accordance with said logic signals and said waveform convention.
Claim 2
Independent Claim
124 words
A system for exercising integrated circuits, comprising: a plurality of counters, means for specifying a counting function of each of said plurality of counters, means for providing ordered nesting of counting of said plurality of counters, means for simultaneously storing a plurality of macros, each of said macros combining outputs of said plurality of counters in a predetermined manner, means for selecting one of said plurality of macros, means for forming logic signals from the outputs of said plurality of counters in accordance with said selected macro, means for specifying a waveform convention in accordance with each of said logic signals, and means for outputting a vector as an input to an integrated circuit in accordance with said logic signals and said waveform convention.
Claim 3
Dependent Claim
14 words
A system as recited in claim 1, further including means for compressing said vector.
Claim 4
Dependent Claim
24 words
A system as recited in claim 1 further including means for associating each bit of said vector with a pin of said integrated circuit.
Claim 5
Dependent Claim
33 words
A system as recited in claim 1, further including means for generating a clock signal, and means for gating said clock signal to a channel included in said input to said integrated circuit.
Claim 6
Independent Claim
109 words
A method for exercising integrated circuits including the steps of: specifying a counting function of each of a plurality of counters, providing ordered nesting of counting of said plurality of counters, storing, simultaneously, a plurality of macros, each of said macros combining outputs of said plurality of counters in a predetermined manner, selecting one of said plurality of macros, forming logic signals from the outputs of said plurality of counters in accordance with said selected macro, specifying a waveform convention in accordance with each of said logic signals, and outputting a vector as an input to an integrated circuit in accordance with said logic signals and said waveform convention.
Claim 7
Independent Claim
109 words
A method for exercising integrated circuits including the steps of: specifying a counting function of each of a plurality of counters, providing ordered nesting of counting of said plurality of counters, storing, simultaneously, a plurality of macros, each of said macros combining outputs of said plurality of counters in a predetermined manner, selecting one of said plurality of macros, forming logic signals from the outputs of said plurality of counters in accordance with said selected macro, specifying a waveform convention in accordance with each of said logic signals, and outputting a vector as an input to an integrated circuit in accordance with said logic signals and said waveform convention.
Claim 8
Dependent Claim
15 words
A method as recited in claim 5, further including the step of compressing said vector.
Claim 9
Dependent Claim
25 words
A method as recited in claim 5 further including the step of associating each bit of said vector with a pin of said integrated circuit.
Claim 10
Dependent Claim
32 words
A method as recited in claim 5, further including the steps of generating a clock signal, and gating said clock signal to a channel included in said input to said integrated circuit.
Claim 11
Dependent Claim
19 words
The system of claim 1, wherein said outputting means outputs said vector for testing operability of said integrated circuit.
Claim 12
Dependent Claim
12 words
The system of claim 1, wherein said plurality of counters equals six.
Claim 13
Dependent Claim
21 words
The method of claim 5, wherein said vector is input into an integrated circuit for testing operability of the integrate circuit.
Claim 14
Dependent Claim
46 words
The method of claim 11 wherein said selected macro combines the outputs of said counters to form a plurality of patterns; storing said plurality of patterns in a memory; and reading said plurality of patterns from said memory in a predefined sequence to form said vector.
Claim 15
Independent Claim
123 words
A system for exercising integrated circuits, comprising: a plurality of counters; a circuit which specifies a counting function for each of said plurality of counters; a circuit which nests counting of said plurality of counters according to a predetermined order; a circuit which simultaneously stores a plurality of macros, each of said macros combining outputs of said plurality of counters in a predetermined manner, a circuit which selects one of said plurality of macros, a circuit which forms logic signals from outputs of said plurality of counters in accordance with said selected macro, a circuit which specifies a waveform; and a circuit which derives a vector for testing an integrated circuit, said vector being derived based on said logic signals and said waveform.
Claim 16
Independent Claim
123 words
A system for exercising integrated circuits, comprising: a plurality of counters; a circuit which specifies a counting function for each of said plurality of counters; a circuit which nests counting of said plurality of counters according to a predetermined order; a circuit which simultaneously stores a plurality of macros, each of said macros combining outputs of said plurality of counters in a predetermined manner, a circuit which selects one of said plurality of macros, a circuit which forms logic signals from outputs of said plurality of counters in accordance with said selected macro, a circuit which specifies a waveform; and a circuit which derives a vector for testing an integrated circuit, said vector being derived based on said logic signals and said waveform.
Claim 17
Dependent Claim
49 words
The system of claim 13, further comprising: a circuit which combines the outputs of said plurality of counters to form a plurality of patterns: a memory for storing said plurality of patterns; and a circuit which reads said plurality of patterns from said memory according to a predefined sequence.
Claim 18
Dependent Claim
58 words
A system as recited in claim 1, further comprising: means for pre-programming said plurality of macros, said pre-programming means including interface means for allowing one or more parameters of at least one of said plurality of macros to be entered by a user so that the outputs of said plurality of counters are combined in said predetermined manner.
Claim 19
Dependent Claim
44 words
A system as recited in claim 1, wherein said selecting means combines the outputs of said plurality of counters to form a plurality of patterns, and wherein said forming means includes means for reading out said patterns from a memory in a predefined sequence.
Claim 20
Dependent Claim
53 words
A method as recited in claim 5, further comprising: pre-programming said plurality of macros in accordance with steps which include allowing a user to alter at least one parameter of at least one of said plurality of macros so that the outputs of said plurality of counters are combined in said predetermined manner.
Claim 21
Dependent Claim
47 words
A system as recited in claim 13, further comprising: an interface for allowing one or more parameters of at least one of said plurality of macros to be entered by a user so that the outputs of said plurality of counters are combined in said predetermined manner.
References Cited (Backward Citations)
US4586181A
Cited
US4682330A
Cited
US4754215A
Cited
US4994732A
Cited
US5010552A
Cited
US5097468A
Cited
US5072178A
Cited
US5271015A
Cited
US5285453A
Cited
US5479415A
Cited
US5430736A
Cited
US5453995A
Cited
US5475624A
Cited
US5499250A
Cited
US5499248A
Cited
US5524114A
Cited
US5563526A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |