Method and apparatus for generating test pattern for sequential logic circuit of integrated circuit

Claim 1

An apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said apparatus comprising: first input value generating means of generating a combination of first external input values so that a transition process is performed from a second state of said plurality of storage elements to a first state thereof; first state generating-means for generating a third state different from said second state by a predetermined natural number of bits; second input value generating means for generating a combination of second external input values so that a transition process is performed from a third state of said plurality of storage elements to said first state thereof; second state generating means for generating a fourth state other than said first to third states; third input value generating means for generating a combination of third external input values so that a transition process is performed from a fourth state of said plurality of storage elements to said first state thereof; first setting means for setting said fourth state as said first state; storage means for storing name data of storage elements corresponding to bits of different states between said second and third states; second setting means for setting said third state as said first state; scan request degree increasing means for increasing a degree of requesting a scan operation for each of said storage elements, name data of which have been stored in said storage means; scan storage element selecting means for selecting storage elements to be scanned based on said degree of requesting the scan operation; scan converting means for converting said storage elements selected by said scan storage element selecting means into scan storage elements; and test pattern generating means for generating a test pattern for said sequential logic circuit when said storage elements selected by said scan storage element selecting means are converted into scan storage elements by said scan converting means.

Claim 2

An apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said apparatus comprising: first input value generating means of generating a combination of first external input values so that a transition process is performed from a second state of said plurality of storage elements to a first state thereof; first state generating-means for generating a third state different from said second state by a predetermined natural number of bits; second input value generating means for generating a combination of second external input values so that a transition process is performed from a third state of said plurality of storage elements to said first state thereof; second state generating means for generating a fourth state other than said first to third states; third input value generating means for generating a combination of third external input values so that a transition process is performed from a fourth state of said plurality of storage elements to said first state thereof; first setting means for setting said fourth state as said first state; storage means for storing name data of storage elements corresponding to bits of different states between said second and third states; second setting means for setting said third state as said first state; scan request degree increasing means for increasing a degree of requesting a scan operation for each of said storage elements, name data of which have been stored in said storage means; scan storage element selecting means for selecting storage elements to be scanned based on said degree of requesting the scan operation; scan converting means for converting said storage elements selected by said scan storage element selecting means into scan storage elements; and test pattern generating means for generating a test pattern for said sequential logic circuit when said storage elements selected by said scan storage element selecting means are converted into scan storage elements by said scan converting means.

Claim 7

An apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said apparatus comprising: input value generating means for generating a combination of external input values so that effects of a fault of said sequential logic circuit reach external output terminals thereof; storage element selecting means for selecting storage elements, states of which are necessary to be changed in order that the effects of the fault of said sequential logic circuit reach said external output terminals thereof; storage means for storing said storage elements selected by said storage element selecting means; scan request degree increasing means for increasing degree of requesting a scan operation for each of said storage elements, name data of which have been stored in said storage means; scan storage element selecting means for selecting storage elements to be scanned based on said degree requesting the scan operation; scan converting means for converting said storage elements selected by said scan storage element selecting means into scan storage elements; and test pattern generating means for generating a test pattern for said sequential logic circuit when said storage elements selected by said scan storage element selecting means are converted into scan storage elements by said scan converting means, wherein said input value generating means, said storage element means selecting means and said storage means are made to operate a plurality of times for a plurality of faults in said sequential logic circuit, wherein scan storage element selecting means comprises: calculating means for calculating each testability cost of said sequential logic circuit required for testing said sequential logic circuit when each of a plurality of storage elements each having the maximum degree of requesting the scan operation is converted into a scan storage element; testability cost selecting means for selecting the minimum testability cost among the testability costs calculated by said calculating means; and element selecting means for selecting a storage element corresponding to the minimum testability cost selected by said testability cost selecting means.

Claim 8

An apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said apparatus comprising: input value generating means for generating a combination of external input values so that effects of a fault of said sequential logic circuit reach external output terminals thereof; storage element selecting means for selecting storage elements, states of which are necessary to be changed in order that the effects of the fault of said sequential logic circuit reach said external output terminals thereof; storage means for storing said storage elements selected by said storage element selecting means; scan request degree increasing means for increasing degree of requesting a scan operation for each of said storage elements, name data of which have been stored in said storage means; scan storage element selecting means for selecting storage elements to be scanned based on said degree requesting the scan operation; scan converting means for converting said storage elements selected by said scan storage element selecting means into scan storage elements; and test pattern generating means for generating a test pattern for said sequential logic circuit when said storage elements selected by said scan storage element selecting means are converted into scan storage elements by said scan converting means, wherein said input value generating means, said storage element means selecting means and said storage means are made to operate a plurality of times for a plurality of faults in said sequential logic circuit, wherein scan storage element selecting means comprises: calculating means for calculating each testability cost of said sequential logic circuit required for testing said sequential logic circuit when each of a plurality of storage elements each having the maximum degree of requesting the scan operation is converted into a scan storage element; testability cost selecting means for selecting the minimum testability cost among the testability costs calculated by said calculating means; and element selecting means for selecting a storage element corresponding to the minimum testability cost selected by said testability cost selecting means.

Claim 9

An apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements, comprising: calculating means for calculating each testability cost of said sequential logic circuit required for testing said sequential logic circuit when each of a plurality of storage elements is converted into a scan storage element; testability cost selecting means for selecting the minimum testability cost among the testability costs calculated by said calculating means; storage element selecting means for selecting a storage element corresponding to the minimum testability cost selected by said testability cost selecting means; scan converting means for converting said storage elements selected by said storage element selecting means into scan storage elements; and test pattern generating means for generating a test pattern for said sequential logic circuit when said storage elements selected by said scan storage element selecting means are converted into scan storage element by said scan converting means.

Claim 10

An apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements, comprising: calculating means for calculating each testability cost of said sequential logic circuit required for testing said sequential logic circuit when each of a plurality of storage elements is converted into a scan storage element; testability cost selecting means for selecting the minimum testability cost among the testability costs calculated by said calculating means; storage element selecting means for selecting a storage element corresponding to the minimum testability cost selected by said testability cost selecting means; scan converting means for converting said storage elements selected by said storage element selecting means into scan storage elements; and test pattern generating means for generating a test pattern for said sequential logic circuit when said storage elements selected by said scan storage element selecting means are converted into scan storage element by said scan converting means.

Claim 14

An apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said apparatus comprising: fault selecting means for selecting a fault among a plurality of faults of said sequential logic circuit; test pattern generating means for generating a test pattern for said fault selected by said fault selecting means; state storage means for storing both of states of said plurality of storage elements when storage elements to be scanned are scanned-in and states of said plurality of storage elements when said storage elements to be scanned are not scanned-in in the case that said test pattern is generated by said test pattern generating means; scan storage element selecting means for selecting a storage element to be scanned among said storage elements to be scanned in the case that said test pattern is generated by said test patter generating means; scan converting means for converting said storage element selected by said storage element selecting means into scan storage elements; and test pattern generating means for generating a test pattern for said sequential logic circuit when said storage elements selected by said scan storage element selecting means are converted into scan storage elements by said scan converting means, based on said states thereof stored in said storage means.

Claim 15

An apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said apparatus comprising: fault selecting means for selecting a fault among a plurality of faults of said sequential logic circuit; test pattern generating means for generating a test pattern for said fault selected by said fault selecting means; state storage means for storing both of states of said plurality of storage elements when storage elements to be scanned are scanned-in and states of said plurality of storage elements when said storage elements to be scanned are not scanned-in in the case that said test pattern is generated by said test pattern generating means; scan storage element selecting means for selecting a storage element to be scanned among said storage elements to be scanned in the case that said test pattern is generated by said test patter generating means; scan converting means for converting said storage element selected by said storage element selecting means into scan storage elements; and test pattern generating means for generating a test pattern for said sequential logic circuit when said storage elements selected by said scan storage element selecting means are converted into scan storage elements by said scan converting means, based on said states thereof stored in said storage means.

Claim 19

A method of generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said method including steps of: generating a combination of first external input values so that a transition process is performed from a second state of said plurality of storage elements to a first state thereof; generating a third state different from said second state by a predetermined natural number of bits; generating a combination of second external input values so that a transition process is performed from a third state of said plurality of storage elements to said first state thereof; generating a fourth state other than said first to third states; generating a combination of third external input values so that a transition process is performed from a fourth state of said plurality of storage elements to said first state thereof; setting said fourth state as said first state; storing in storage means name data of storage elements corresponding to bits of different states between said second and third states; setting said third stage as said first state; increasing a degree of requesting a scan operation for each of said storage elements, name data of which have been stored in said storage means; selecting storage elements to be scanned based on said degree of requesting the scan operation; converting said selected storage elements into scan storage elements; and generating a test pattern for said sequential logic circuit when said selected storage elements are converted into scan storage elements.

Claim 20

A method of generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said method including steps of: generating a combination of first external input values so that a transition process is performed from a second state of said plurality of storage elements to a first state thereof; generating a third state different from said second state by a predetermined natural number of bits; generating a combination of second external input values so that a transition process is performed from a third state of said plurality of storage elements to said first state thereof; generating a fourth state other than said first to third states; generating a combination of third external input values so that a transition process is performed from a fourth state of said plurality of storage elements to said first state thereof; setting said fourth state as said first state; storing in storage means name data of storage elements corresponding to bits of different states between said second and third states; setting said third stage as said first state; increasing a degree of requesting a scan operation for each of said storage elements, name data of which have been stored in said storage means; selecting storage elements to be scanned based on said degree of requesting the scan operation; converting said selected storage elements into scan storage elements; and generating a test pattern for said sequential logic circuit when said selected storage elements are converted into scan storage elements.

Claim 25

A method of generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said method including steps of: generating a combination of external input values so that effects of a fault of said sequential logic circuit reach external output terminals thereof; selecting storage elements, states of which are necessary to be changed in order that the effects of the fault of said sequential logic circuit reach said external output terminals thereof; storing said selected storage elements in storage means; increasing a degree of requesting a scan operation for each said storage elements, name data of which have been stored in said storage means; selecting storage elements to be scanned based on said degree of requesting the scan operation; converting said selected storage elements into scan storage elements; and generating a test pattern for said sequential logic circuit when said selected storage elements selected are converted into scan storage elements, wherein said external input values generating step, said storage elements selecting step and said storing step are performed a plurality of times for a plurality of faults in said sequential logic circuit, wherein scan storage element selecting step includes steps of; calculating each testability cost of said sequential logic circuit required for testing said sequential logic circuit when each of a plurality of storage elements each having the maximum degree of requesting the scan operation is converted into a scan storage element; selecting the minimum testability cost among the calculated testability costs; and selecting a storage element corresponding to the selected minimum testability cost.

Claim 26

A method of generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said method including steps of: generating a combination of external input values so that effects of a fault of said sequential logic circuit reach external output terminals thereof; selecting storage elements, states of which are necessary to be changed in order that the effects of the fault of said sequential logic circuit reach said external output terminals thereof; storing said selected storage elements in storage means; increasing a degree of requesting a scan operation for each said storage elements, name data of which have been stored in said storage means; selecting storage elements to be scanned based on said degree of requesting the scan operation; converting said selected storage elements into scan storage elements; and generating a test pattern for said sequential logic circuit when said selected storage elements selected are converted into scan storage elements, wherein said external input values generating step, said storage elements selecting step and said storing step are performed a plurality of times for a plurality of faults in said sequential logic circuit, wherein scan storage element selecting step includes steps of; calculating each testability cost of said sequential logic circuit required for testing said sequential logic circuit when each of a plurality of storage elements each having the maximum degree of requesting the scan operation is converted into a scan storage element; selecting the minimum testability cost among the calculated testability costs; and selecting a storage element corresponding to the selected minimum testability cost.

Claim 27

A method of generating a test pattern for sequential logic circuit including a plurality of storage elements, including steps of: calculating each testability cost of said sequential logic circuit required for testing said sequential logic circuit when each of a plurality of storage elements is converted into a scan storage element; selecting the minimum testability cost among the calculated testability costs; selecting a storage element corresponding to the selected minimum testability cost; converting said selected storage elements into scan storage elements; and generating a test pattern for said sequential logic circuit when said selected storage elements are converted into scan storage elements.

Claim 28

A method of generating a test pattern for sequential logic circuit including a plurality of storage elements, including steps of: calculating each testability cost of said sequential logic circuit required for testing said sequential logic circuit when each of a plurality of storage elements is converted into a scan storage element; selecting the minimum testability cost among the calculated testability costs; selecting a storage element corresponding to the selected minimum testability cost; converting said selected storage elements into scan storage elements; and generating a test pattern for said sequential logic circuit when said selected storage elements are converted into scan storage elements.

Claim 32

A method of generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said method including steps of: selecting a fault among a plurality of faults of said sequential logic circuit; generating a test pattern for said selected fault; storing both of states of said plurality of storage elements in storage means when storage elements to be scanned are scanned-in and states of said plurality of storage elements when said storage elements to be scanned are not scanned-in in the case that said test pattern is generated; selecting a storage element to be scanned among said storage elements to be scanned in the case that said test pattern is generated; converting said selected storage element into scan storage elements; and generating a test pattern for said sequential logic circuit when said selected storage elements are converted into scan storage elements, based on said states thereof stored in said storage means.

Claim 33

A method of generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit, logical values of bits of said plurality of storage elements being represented by a state, said method including steps of: selecting a fault among a plurality of faults of said sequential logic circuit; generating a test pattern for said selected fault; storing both of states of said plurality of storage elements in storage means when storage elements to be scanned are scanned-in and states of said plurality of storage elements when said storage elements to be scanned are not scanned-in in the case that said test pattern is generated; selecting a storage element to be scanned among said storage elements to be scanned in the case that said test pattern is generated; converting said selected storage element into scan storage elements; and generating a test pattern for said sequential logic circuit when said selected storage elements are converted into scan storage elements, based on said states thereof stored in said storage means.