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US4586181A
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Test pattern generating apparatus
Assignee: TAKEDA RIKEN Co Ltd 1-32-1 ASAHI-CHO NERIMA-KU TOKYO 176 JAPAN A CORP OF
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Filing: 1983-11-14
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Granted: 1986-04-29
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Expires: 2003-11-14
Abstract
Abstract A test pattern generator includes means for reading out a plurality of memories non-successively while outputting the test patterns stored identically in the addresses of the memories, such as for sequentially repeating the test patterns that are provided to a logic circuit being tested. The sequence of test patterns is determined by a series of instructions which are accessed by a program counter, and the instructions can cause a jump in the counting of the program counter, for instance to repeat addresses of the memories for repeating a desired sequence of test patterns a predetermined number of times. The timing of the addressing of the memories for the reading out of the test patterns can be faster than the timing for writing the test patterns into the memories for storage.
Inventors
- 👤 Masao Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:40
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
169 words
A test pattern generating apparatus for generating a test pattern for testing a logic circuit, comprising an address generator for generating a series of desired addresses in synchronism with a clock signal, a plurality of pattern data memories for storing pattern data for generating the test pattern, said pattern data memories have the same pattern data stored in the same respective addresses, a plurality of registers for respectively accessing in succession different ones of said pattern data memories by the addresses from the address generator, selection means for selectively taking out the pattern data from said accessed pattern data memories, and means for providing an address clock alternately to the plurality of registers, in a respective succession corresponding to said accessing of said pattern data memories, when said pattern data is to be read out from said pattern data memories, and for providing an address clock of the same timing commonly to the plurality of registers when said pattern data is to be written into said pattern data memories.
Claim 2
Dependent Claim
169 words
A test pattern generating apparatus for generating a test pattern for testing a logic circuit, comprising an address generator for generating a series of desired addresses in synchronism with a clock signal, a plurality of pattern data memories for storing pattern data for generating the test pattern, said pattern data memories have the same pattern data stored in the same respective addresses, a plurality of registers for respectively accessing in succession different ones of said pattern data memories by the addresses from the address generator, selection means for selectively taking out the pattern data from said accessed pattern data memories, and means for providing an address clock alternately to the plurality of registers, in a respective succession corresponding to said accessing of said pattern data memories, when said pattern data is to be read out from said pattern data memories, and for providing an address clock of the same timing commonly to the plurality of registers when said pattern data is to be written into said pattern data memories.
Claim 3
Dependent Claim
36 words
The apparatus of claim 1, comprising means for providing address load pulses with the frequency of said clock signal to the plurality of registers when writing the pattern data into the plurality of pattern data memories.
Claim 4
Dependent Claim
46 words
The apparatus of claim 2, wherein said clock for said reading out of pattern data memories comprises clock pulses that occur at a rate that is faster than the rate of said address load pulses for said writing of pattern data into said pattern data memories.
Claim 5
Dependent Claim
34 words
The apparatus of claim 3, wherein said clock pulses of said address clock are faster than said address load pulses by a factor equal to the number of said plurality of pattern data memories.
Claim 6
Dependent Claim
26 words
The apparatus of claim 2, 3 or 4, wherein all of said pattern data memories have the same pattern data stored in the same respective addresses.
Claim 7
Dependent Claim
69 words
The apparatus of claim 1, 2, 3 or 4, wherein said address generator includes a program counter for generating said addresses by incrementing from an initial address supplied thereto, and an instruction memory having addresses corresponding to the addresses of said pattern data memories, wherein the instruction memory is accessed by said addresses generated by said program counter to provide selected jumping in the counting of said program counter.
Claim 8
Dependent Claim
53 words
The apparatus of claim 6, wherein said addresses of said instruction memory selectively store an operating code for indicating whether said incrementing or said jumping of said program counter is to occur and an operand for providing the address to which said jumping in the counting of said program counter is to occur.
Claim 9
Dependent Claim
80 words
The apparatus of claim 7, said address generator comprising a status control and an index counter, wherein said operand of the address provided by said program counter is provided to said program counter, and the operating code of the address of the instruction memory being accessed by said program counter is provided to said status control, so that a load command is provided from said status control to said program counter to take in the respective operand for said jumping.
Claim 10
Dependent Claim
67 words
The apparatus of claim 8, wherein said addresses of said instruction memory generated by said program counter, selectively provide an operating code indicating a set index instruction, before providing each said jump instruction, and the operand of the respective address of said set index instruction is provided to said status control to control the number of times the respective jumping of said program counter is to occur.
Claim 11
Dependent Claim
35 words
The apparatus of claim 1, wherein said test pattern is selectively provided with repeated portions corresponding to the same pattern data being selected by said selection means from different ones of said pattern data memories.
Claim 12
Dependent Claim
39 words
The apparatus of claim 1, wherein said selective taking out of pattern data from said pattern data memories by said selection means corresponds to said providing of said address clock to said pattern data memories in said respective succession.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |