Self repairing integrated circuit memory devices and methods

Claim 2

An integrated circuit memory device, comprising: a plurality of normal memory cells; a plurality of spare memory cells; a plurality of spare substituting circuits, each of which is responsive to a defective normal memory cell address which is programmed therein, and which substitutes at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address which is programmed therein; and sequential spare substituting circuit selecting means, connected to said plurality of spare substituting circuits and responsive to a defect indication signal from external to said integrated circuit memory device, for sequentially selecting a respective one of said spare circuits for programming with sequential ones of defective normal memory cell addresses.

Claim 3

An integrated circuit memory device according to claim 1 wherein said sequential spare substituting circuit selecting means further comprises: means for generating an alarm signal in response to a last one of said plurality of spare substituting circuits being sequentially selected.

Claim 4

An integrated circuit memory device according to claim 1: wherein said plurality of normal memory cells are arranged in an array having a plurality of normal memory cell rows and a plurality of normal memory cell columns; wherein said plurality of spare memory cells comprise a plurality of spare memory cell rows and a plurality of spare memory cell columns; wherein said plurality of spare substituting circuits comprise a plurality of row substituting circuits each of which is responsive to a defective normal memory cell row address which is programmed therein, and which substitutes a spare memory cell row for a normal memory cell row including a defective memory cell which is located at the defective normal memory cell row address which is programmed therein, and a plurality of column substituting circuits each of which is responsive to a defective normal memory cell column address which is programmed therein, and which substitutes a spare memory cell column for a normal memory cell column including a defective memory cell which is located at the defective normal memory cell column address which is programmed therein; and wherein said sequential spare substituting circuit selecting means comprises sequential spare row selecting means for sequentially selecting a respective one of said row substituting circuits for programming with sequential ones of defective normal memory cell row addresses, and sequential spare column selecting means for sequentially selecting a respective one of said column substituting circuits for programming with sequential ones of defective normal memory cell column addresses.

Claim 5

An integrated circuit memory device according to claim 3 wherein said sequential spare substituting circuit selecting means further comprises: means, responsive to said defect indicating signal indicating a defect in at least two normal memory cells in different rows and a same column, for activating a sequential spare column selecting means for programming with the address of the same column.

Claim 6

An integrated circuit memory device according to claim 1 in combination with: a memory device tester, which is external to said memory device, and which sequentially tests memory cells at selected memory cell addresses, and which provides the defect indicating signal to said sequential spare substituting circuit selecting means upon detecting a defective memory cell at the selected memory cell address.

Claim 7

An integrated circuit memory device according to claim 3 wherein said sequential spare substituting circuit selecting means further comprises: means, responsive to an indication that a last one of said plurality of row substituting circuits has been programmed, for sequentially selecting a respective one of said column substituting circuits.

Claim 8

An integrated circuit memory device according to claim 1 wherein each of said spare substituting circuits comprises: a plurality of electrically programmable fuses; and means responsive to a defective normal memory cell address which is applied thereto, and to said sequential spare substituting circuit selecting means, for programming said plurality of electrically programmable fuses with said defective normal memory cell address upon selection of said spare substituting circuit by said sequential spare substituting circuit selecting means.

Claim 9

An integrated circuit memory device according to claim 7: wherein said plurality of electrically programmable fuses comprise a plurality of elongated fuses, each having a central portion and a pair of fuse ends which are wider than said central portion; and wherein said programming means comprises current supplying means, for supplying current through the elongated fuses which correspond to said defective normal memory cell address, to thereby open the elongated fuses which correspond to said defective normal memory cell address.

Claim 10

An integrated circuit memory device according to claim 8: wherein said plurality of elongated fuses comprise a plurality of polycrystalline silicon elongated fuses.

Claim 11

An integrated circuit memory device, comprising: a plurality of normal memory cells; a plurality of spare memory cells; a plurality of spare substituting circuits, each of which is responsive to a defective normal memory cell address which is programmed therein, and which substitutes at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address which is programmed therein; and spare substituting circuit selecting means, connected to said plurality of spare substituting circuits and which is responsive to a defect indication signal from external to said integrated circuit memory device, for selecting one of said spare circuits for programming with a defective normal memory cell addresses; wherein each of said spare substituting circuits comprises: a plurality of electrically programmable fuses; and means responsive to a defective normal memory cell address which is applied thereto, and to said spare substituting circuit, for programming said plurality of electrically programmable fuses with said defective normal memory cell address upon selection of said spare substituting circuit by said spare substituting circuit selecting means.

Claim 12

An integrated circuit memory device, comprising: a plurality of normal memory cells; a plurality of spare memory cells; a plurality of spare substituting circuits, each of which is responsive to a defective normal memory cell address which is programmed therein, and which substitutes at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address which is programmed therein; and spare substituting circuit selecting means, connected to said plurality of spare substituting circuits and which is responsive to a defect indication signal from external to said integrated circuit memory device, for selecting one of said spare circuits for programming with a defective normal memory cell addresses; wherein each of said spare substituting circuits comprises: a plurality of electrically programmable fuses; and means responsive to a defective normal memory cell address which is applied thereto, and to said spare substituting circuit, for programming said plurality of electrically programmable fuses with said defective normal memory cell address upon selection of said spare substituting circuit by said spare substituting circuit selecting means.

Claim 13

An integrated circuit memory device according to claim 10 wherein said spare substituting circuit selecting means further comprises: means for generating an alarm signal in response to a last one each of said plurality of spare substituting circuits being selected.

Claim 14

An integrated circuit memory device according to claim 10: wherein said plurality of normal memory cells are arranged in an array having a plurality of normal memory cell rows and a plurality of normal memory cell columns; wherein said plurality of spare memory cells comprise a plurality of spare memory cell rows and a plurality of spare memory cell columns; wherein said plurality of spare substituting circuits comprise a plurality of row substituting circuits each of which is responsive to a defective normal memory cell row address which is programmed therein, and which substitutes a spare memory cell row for a normal memory cell row including a defective memory cell which is located at the defective normal memory cell row address which is programmed therein, and a plurality of column substituting circuits each of which is responsive to a defective normal memory cell column address which is programmed therein, and which substitutes a spare memory cell column for a normal memory cell column including a defective memory cell which is located at the defective normal memory cell column address which is programmed therein; and wherein said spare substituting circuit selecting means comprises spare row selecting means for selecting one of said row substituting circuits for programming with a defective normal memory cell row address, and spare column selecting means for selecting one of said column substituting circuits for programming with a defective normal memory cell column address.

Claim 15

An integrated circuit memory device according to claim 12 wherein said spare substituting circuit selecting means further comprises: means, responsive to said defect indicating signal indicating a defect in at least two normal memory cells in different rows and a same column, for activating a spare column selecting means for programming with the address of the same column.

Claim 16

An integrated circuit memory device according to claim 10 in combination with: a memory device tester, which is external to said memory device, and which sequentially tests memory cells at selected memory cell addresses, and which provides the defect indicating signal to said spare substituting circuit selecting means upon detecting a defective memory cell at the selected memory cell address.

Claim 17

An integrated circuit memory device according to claim 12 wherein said spare substituting circuit selecting means further comprises: means, responsive to an indication that a last ones of said plurality of row substituting circuits has been programmed, for selecting a respective one of said column substituting circuits.

Claim 18

An integrated circuit memory device according to claim 10: wherein said plurality of electrically programmable fuses comprise a plurality of elongated fuses, each having a central portion and a pair of fuse ends which are wider than said central portion; and wherein said programming means comprises current supplying means, for supplying current through the elongated fuses which correspond to said defective normal memory cell address, to thereby open the elongated fuses which correspond to said defective normal memory cell address.

Claim 19

An integrated circuit memory device according to claim 16: wherein said plurality of elongated fuses comprise a plurality of polycrystalline silicon elongated fuses.

Claim 20

An integrated circuit memory device, comprising: a plurality of normal memory cells; a plurality of spare memory cells; a plurality of spare substituting circuits, each of which is responsive to a defective normal memory cell address which is programmed therein, and which substitutes at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address which is programmed therein; and spare substituting circuit selecting means, connected to said plurality of spare substituting circuits and which is responsive to a defect indication signal from external to said integrated circuit memory device, for selecting one of said spare circuits for programming with a defective normal memory cell addresses; and for transmitting an alarm signal to external of said integrated circuit device in response to each of said plurality of spare substituting circuits being selected.

Claim 21

An integrated circuit memory device, comprising: a plurality of normal memory cells; a plurality of spare memory cells; a plurality of spare substituting circuits, each of which is responsive to a defective normal memory cell address which is programmed therein, and which substitutes at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address which is programmed therein; and spare substituting circuit selecting means, connected to said plurality of spare substituting circuits and which is responsive to a defect indication signal from external to said integrated circuit memory device, for selecting one of said spare circuits for programming with a defective normal memory cell addresses; and for transmitting an alarm signal to external of said integrated circuit device in response to each of said plurality of spare substituting circuits being selected.

Claim 22

An integrated circuit memory device according to claim 18: wherein said plurality of normal memory cells are arranged in an array having a plurality of normal memory cell rows and a plurality of normal memory cell columns; wherein said plurality of spare memory cells comprise a plurality of spare memory cell rows and a plurality of spare memory cell columns; wherein said plurality of spare substituting circuits comprise a plurality of row substituting circuits each of which is responsive to a defective normal memory cell row address which is programmed therein, and which substitutes a spare memory cell row for a normal memory cell row including a defective memory cell which is located at the defective normal memory cell row address which is programmed therein, and a plurality of column substituting circuits each of which is responsive to a defective normal memory cell column address which is programmed therein, and which substitutes a spare memory cell column for a normal memory cell column including a defective memory cell which is located at the defective normal memory cell column address which is programmed therein; and wherein said spare substituting circuit selecting means comprises spare row selecting means for selecting one of said row substituting circuits for programming with a defective normal memory cell row address, and spare column selecting means for selecting one of said column substituting circuits for programming with a defective normal memory cell column address.

Claim 23

An integrated circuit memory device according to claim 19 wherein said spare substituting circuit selecting means further comprises: means, responsive to said defect indicating signal indicating a defect in at least two normal memory cells in different rows and a same column, for activating a spare column selecting means for programming with the address of the same column.

Claim 24

An integrated circuit memory device according to claim 18 in combination with: a memory device tester, which is external to said memory device, and which sequentially tests memory cells at selected memory cell addresses, and which provides the defect indicating signal to said spare substituting circuit selecting means upon detecting a defective memory cell at the selected memory cell address.

Claim 25

An integrated circuit memory device according to claim 18 wherein said spare substituting circuit selecting means further comprises: means, responsive to an indication that a last one of said plurality of row substituting circuits has been programmed, for selecting a respective one of said column substituting circuits.

Claim 26

An integrated circuit memory device, comprising: a plurality of normal memory cells arranged in an array having a plurality of normal memory cell rows and a plurality of normal memory cell columns; a plurality of spare memory cell rows; a plurality of spare memory cell columns; a plurality of row substituting circuits each of which is responsive to a defective normal memory cell row address which is programmed therein, and which substitutes a spare memory cell row for a normal memory cell row including a defective memory cell which is located at the defective normal memory cell row address which is programmed therein; a plurality of column substituting circuits each of which is responsive to a defective normal memory cell column address which is programmed therein, and which substitutes a spare memory cell column for a normal memory cell column including a defective memory cell which is located at the defective normal memory cell column address which is programmed therein; spare row selecting means for selecting one of said row substituting circuits for programming with a defective normal memory cell row address; spare column selecting means for selecting one of said column substituting circuits for programming with a defective normal memory cell column address; and means, responsive to defect indicating signals from external to said memory device, and which indicate a defect in two normal memory cells in different rows and a same column, for activating a spare column selecting means for programming with the address of the same column.

Claim 27

An integrated circuit memory device, comprising: a plurality of normal memory cells arranged in an array having a plurality of normal memory cell rows and a plurality of normal memory cell columns; a plurality of spare memory cell rows; a plurality of spare memory cell columns; a plurality of row substituting circuits each of which is responsive to a defective normal memory cell row address which is programmed therein, and which substitutes a spare memory cell row for a normal memory cell row including a defective memory cell which is located at the defective normal memory cell row address which is programmed therein; a plurality of column substituting circuits each of which is responsive to a defective normal memory cell column address which is programmed therein, and which substitutes a spare memory cell column for a normal memory cell column including a defective memory cell which is located at the defective normal memory cell column address which is programmed therein; spare row selecting means for selecting one of said row substituting circuits for programming with a defective normal memory cell row address; spare column selecting means for selecting one of said column substituting circuits for programming with a defective normal memory cell column address; and means, responsive to defect indicating signals from external to said memory device, and which indicate a defect in two normal memory cells in different rows and a same column, for activating a spare column selecting means for programming with the address of the same column.

Claim 28

An integrated circuit memory device according to claim 23 further comprising: means for generating an alarm signal in response to a last one of said plurality of row and column substituting circuits being selected.

Claim 29

An integrated circuit memory device according to claim 23 further comprising: means, responsive to an indication that a last ones of said plurality of row substituting circuits has been programmed, for selecting one of said column substituting circuits.

Claim 32

A method according to claim 26 wherein said automatically programming step is followed by the following step which is performed by said memory devices: selecting a second plurality of fuses for programming with a second address of a defective normal memory cell in response to a second defect indicating signal from said memory testing system, to thereby substitute at least one second spare memory cell for at least one second defective normal memory cell which is located at the second defective normal memory cell address.

Claim 33

A method according to claim 27 wherein said step of selecting a second plurality of fuses is followed by the step of: generating an alarm signal if the second plurality of fuses is already programmed.

Claim 34

A method according to claim 26 wherein said plurality of normal memory cells are arranged in an array having a plurality of normal memory cell rows and a plurality of normal memory cell columns, wherein said plurality of spare memory cells comprise a plurality of spare memory cell rows and a plurality of spare memory cell columns, and wherein said step of automatically programming a plurality of fuses comprises the step of: automatically programming a plurality of fuses in the memory device with the column address of the defective normal memory cell in response to the defect indicating signal, if all of said plurality of spare memory cell rows have been substituted for defective normal memory cell rows, to thereby substitute a spare memory cell column for a defective normal memory cell column.

Claim 35

A method according to claim 26 wherein said plurality of normal memory cells are arranged in an array having a plurality of normal memory cell rows and a plurality of normal memory cell columns, wherein said plurality of spare memory cells comprise a plurality of spare memory cell rows and a plurality of spare memory cell columns, and wherein said step of automatically programming a plurality of fuses comprises the step of: automatically programming a plurality of fuses in the memory device with the column address of the defective normal memory cell in response to the defect indicating signal, if two different rows of normal memory cells include a defective memory cell in a same column, to thereby substitute a spare memory cell column for the at least two different rows of normal memory cells including a defective memory cell in a same column.

Claim 36

A method according to claim 26 wherein said step of automatically programming comprises the step of: automatically applying current to the plurality of fuses in the memory device to thereby open the fuses which correspond to the address of the defective normal memory cell in response to the defect indicating signal, to thereby substitute at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address.