Programmable circuit for enabling an associated circuit

Claim 2

An enable circuit for selectively enabling an associated function circuit in response to a first level of an activate signal, the enable circuit comprising: a select circuit that when programmed in a select state and in response to said first level generates on an output line a select signal and conducts substantially zero standby current, and that when programmed in an unselect state and in response to said first level generates on said output line the complement to said select signal and conducts substantially zero standby current; and a latch in communication with said select circuit and said associated function circuit and operable to generate and maintain an enable signal in response to said select signal.

Claim 3

The enable circuit of claim 1 wherein said select circuit comprises: a first switch circuit operable to close in response to said first level of said activate signal; a first selectively conductive element connected in series with said first switch circuit, the series combination of said first switch circuit and said first selectively conductive element being connected between a voltage corresponding to said select signal and the output line of said select circuit, said first selectively conductive element being conductive when said select circuit is programmed in said select state and being non-conductive when said select circuit is programmed in said unselect state; a second switch circuit operable to close in response to said first level of said activate signal; and a second selectively conductive element connected in series with said second switch, the series combination of said second switch circuit and said second selectively conductive element being connected between the output line of said select circuit and a voltage corresponding to the complement to said select signal, said second selectively conductive element being non-conductive when said select circuit is programmed in said select state and being conductive when said select circuit is programmed in said unselect state.

Claim 4

The enable circuit of claim 2 wherein said first selectively conductive element comprises a first fuse circuit that is closed when said select circuit is programmed in said select state and that is open when said select circuit is programmed in said unselect state, and wherein said second selectively conductive element comprises a second fuse circuit that is open when said select circuit is programmed in said select state and closed when said select circuit is programmed in said unselect state.

Claim 5

The enable circuit of claim 3 wherein said first and second fuse circuits each comprise a laser fuse.

Claim 6

The enable circuit of claim 3 wherein said first and second fuse circuits each comprise an electrical fuse.

Claim 9

The method of claim 6 wherein said programming comprises: closing a first switch circuit in response to said first level of said activate signal and opening a second switch circuit serially coupled to said first switch circuit when said select circuit is programmed in said select state; and closing said second switch circuit in response to said first level of said activate signal and opening said first switch circuit when said select circuit is programmed in said unselect state, said select signal being generated on an output terminal between said first and second switch circuits.

Claim 10

The method of claim 7 wherein: said programming a selection circuit in a select state comprises closing a first fuse circuit connected in series with said first switch circuit and said output terminal and opening a second fuse circuit connected in series with said second switch circuit and said output terminal; and said programming a selection circuit in an unselect state comprises opening said first fuse circuit and closing said second fuse circuit.

Claim 11

An enable circuit, coupled to an activate line, for selectively enabling an associated function circuit in response to an enable signal generated in response to an active level of an activate signal, comprising: a zero-standby-current select circuit having a select input terminal coupled to said activate line and having a select output terminal, said select circuit generating an active level of a select signal on said select output terminal in response to said active level of said activate signal when said select circuit is programmed active, and said select circuit generating an inactive level of said select signal on said select output terminal in response to said active level of said activate signal when said select circuit is programmed inactive; a select line coupled to said select output terminal; a latch having a latch input coupled to said select line and a latch output terminal, said latch generating an enable signal in response to said active level of said select signal; and an enable line coupled between said latch output terminal and an enable terminal of said associated function circuit.

Claim 12

An enable circuit, coupled to an activate line, for selectively enabling an associated function circuit in response to an enable signal generated in response to an active level of an activate signal, comprising: a zero-standby-current select circuit having a select input terminal coupled to said activate line and having a select output terminal, said select circuit generating an active level of a select signal on said select output terminal in response to said active level of said activate signal when said select circuit is programmed active, and said select circuit generating an inactive level of said select signal on said select output terminal in response to said active level of said activate signal when said select circuit is programmed inactive; a select line coupled to said select output terminal; a latch having a latch input coupled to said select line and a latch output terminal, said latch generating an enable signal in response to said active level of said select signal; and an enable line coupled between said latch output terminal and an enable terminal of said associated function circuit.

Claim 13

The enable circuit of claim 9 wherein said select circuit comprises: a first switch circuit having a first-switch input terminal coupled to said select input terminal and a first-switch output terminal coupled to said select output terminal; an inverter having an inverter input terminal coupled to said select input terminal and having an inverter output terminal; and a second switch circuit having a second-switch input terminal coupled to said inverter output terminal and a second-switch output terminal coupled to said select output terminal.

Claim 14

The enable circuit of claim 10 wherein: said first switch circuit comprises, a first power-supply terminal, and a first circuit branch coupled between said first power-supply terminal and said first-switch output terminal, said first branch comprising: a first switch having a first control terminal coupled to said first-switch input terminal, and a first fuse circuit serially coupled to said first switch; and said second switch circuit comprises, a second power-supply terminal, and a second circuit branch coupled between said second power-supply terminal and said second-switch output terminal, said second branch circuit comprising: a second switch having a second control terminal coupled to said second-switch input terminal, and a second fuse circuit serially coupled to said second switch.

Claim 15

The enable circuit of claim 11 wherein said first and second fuse circuits each comprise a laser fuse.

Claim 16

The enable circuit of claim 11 wherein said first and second fuse circuits each comprise an electrical fuse.

Claim 17

The enable circuit of claim 11 wherein said first and second switches respectively comprise a P-channel and an N-channel transistor.

Claim 18

The enable circuit of claim 9 wherein said latch comprises: an inverter coupled between said latch input and latch output terminals; and a switch having a control terminal coupled to said latch output terminal and a drive terminal coupled to said latch input terminal.

Claim 19

The enable circuit of claim 15 wherein said switch comprises a P-channel transistor.

Claim 20

The enable circuit of claim 15 wherein said switch comprises an N-channel transistor.

Claim 21

A memory device, comprising: a control circuit operable to generate an activate signal having active and inactive levels; an array of memory cells in communication with said control circuit and arranged in rows and columns; one or more function circuits in communication with said control circuit; one or more enable circuits each in communication with said control circuit and an associated one of said function circuits, each enable circuit comprising, a select circuit that when programmed in a select state and in response to said active level of said activate signal generates a select signal and conducts substantially zero standby current, and that when programmed in an unselect state and in response to said active level of said activate signal generates the complement to said select signal and conducts substantially zero standby current; and a latch in communication with said select circuit and operable to generate and maintain, in response to said select signal, an enable signal for enabling said associated function circuit.

Claim 22

A memory device, comprising: a control circuit operable to generate an activate signal having active and inactive levels; an array of memory cells in communication with said control circuit and arranged in rows and columns; one or more function circuits in communication with said control circuit; one or more enable circuits each in communication with said control circuit and an associated one of said function circuits, each enable circuit comprising, a select circuit that when programmed in a select state and in response to said active level of said activate signal generates a select signal and conducts substantially zero standby current, and that when programmed in an unselect state and in response to said active level of said activate signal generates the complement to said select signal and conducts substantially zero standby current; and a latch in communication with said select circuit and operable to generate and maintain, in response to said select signal, an enable signal for enabling said associated function circuit.

Claim 23

The memory device of claim 18 wherein said select circuit comprises: a first switch circuit operable to close in response to said active level of said activate signal; a first selectively conductive element connected in series with said first switch circuit, the series combination of said first switch circuit and said first selectively conductive element being connected between a voltage corresponding to said select signal and the output line of said select circuit, said first selectively conductive element being conductive when said select circuit is programmed in said select state and being non-conductive when said select circuit is programmed in said unselect state; a second switch circuit operable to close in response to said active level of said activate signal; and a second selectively conductive element connected in series with said second switch, the series combination of said second switch circuit and said second selectively conductive element being connected between said select circuit and a voltage corresponding to the complement to said select signal, said second selectively conductive element being non-conductive when said select circuit is programmed in said select state and being conductive when said select circuit is programmed in said unselect state.

Claim 24

The memory device of claim 19 wherein said first selectively conductive element comprises a first fuse circuit that is closed when said select circuit is programmed in said select state and that is open when said select circuit is programmed in said unselect state, and wherein said second selectively conductive element comprises a second fuse circuit that is open when said select circuit is programmed in said select state and closed when said select circuit is programmed in said unselect state.

Claim 25

The memory device of claim 18, further comprising: a redundant column of memory cells in communication with a corresponding one of said function circuits; and wherein said corresponding function circuit, in response to an enable signal from an associated select circuit, is operable to replace a defective one of said array columns of memory cells with said redundant column.

Claim 26

A programmable selection circuit, comprising: first and second supply terminals; an input terminal coupled to receive an activate signal; an output terminal that provides a selection signal; a first switch having a control terminal coupled to said input terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal; a first fuse circuit having a first fuse terminal coupled to said second switch terminal, and having a second fuse terminal coupled to said output terminal; a second switch having a control terminal coupled to said input terminal, a first switch terminal coupled to said output terminal, and a second switch terminal; and a second fuse circuit having a first fuse terminal coupled to said second switch terminal of said second switch, and having a second fuse terminal coupled to said second supply terminal.

Claim 27

A programmable selection circuit, comprising: first and second supply terminals; an input terminal coupled to receive an activate signal; an output terminal that provides a selection signal; a first switch having a control terminal coupled to said input terminal, a first switch terminal coupled to said first supply terminal, and a second switch terminal; a first fuse circuit having a first fuse terminal coupled to said second switch terminal, and having a second fuse terminal coupled to said output terminal; a second switch having a control terminal coupled to said input terminal, a first switch terminal coupled to said output terminal, and a second switch terminal; and a second fuse circuit having a first fuse terminal coupled to said second switch terminal of said second switch, and having a second fuse terminal coupled to said second supply terminal.

Claim 28

The programmable selection circuit of claim 22, further comprising an inverting circuit that is coupled between said input terminal and said control terminal of said second switch.

Claim 29

The programmable selection circuit of claim 22, further comprising a latch having a latch input terminal coupled to said output terminal, and having a latch output terminal that provides an enable signal.

Claim 30

The programmable selection circuit of claim 22 wherein said first and second fuse circuits each comprise: a third switch having a control terminal, a first switch terminal coupled to said first fuse terminal, and a second switch terminal coupled to said second fuse terminal; a nonvolatile memory cell having a first path terminal coupled to one of said first and second supply terminals, a second path terminal coupled to said control terminal of said third switch, and a control terminal coupled to receive a fuse control signal; and a load device coupled between said second path terminal of said nonvolatile memory cell and the other of said first and second supply terminals.