Programmable interrupt controller, interrupt system and interrupt control process

Claim 2

A programmable interrupt controller for a microprocessor interrupt system, comprising: interrupt request register means, connected to a plurality of interrupt sources through a plurality of interrupt lines and connected to an internal bus, for storing interrupt requests from the interrupt sources; interrupt mask register means, connected to the internal bus, for programmably masking interrupt levels; means for storing a highest priority vector in service, connected to the internal bus; interface means, connected to the internal bus and an external bus, for transmitting the vector stored in the means for storing a highest priority vector in service to the external bus and for simultaneously receiving a signal which is present on the external bus having a priority; and determining means, connected to the interface means, for determining if said highest priority vector in service has a higher priority than the priority of the received signal which is present on the external bus.

Claim 3

A programmable interrupt controller according to claim 1, wherein the determining means, comprises: means for validating a transmission, by the interface means, to the external bus, of a predetermined weight bit of the highest priority vector stored in the means for storing a highest priority vector in service, only if there is equivalence between a bit, one higher in weight then the predetermined weight bit of the highest priority vector in service and a bit, one higher in weight then the predetermined weight bit, of the received signal.

Claim 4

A programmable interrupt controller according to claim 1, wherein the interface means comprises: means for validating transmission of a bit of the highest priority vector in service to the external bus if the bit is in a dominant state and for not validating the transmission if the bit is in a recessive state.

Claim 5

A programmable interrupt controller according to claim 1, further comprising: means for storing a plurality of interrupt vectors, connected to the internal bus, each stored interrupt vector having an interrupt priority and corresponding to one of the interrupt sources; means for comparing, connected to the internal bus, the interrupt priorities, which are stored in said means for storing a plurality of interrupt vectors, of active and non-masked interrupt vectors with a priority of the highest priority vector in service to determine the highest priority vector and loading said means for storing a highest priority vector in service with the determined highest priority vector; sequencer means, connected to the internal bus, for sequentially sending active and non-masked interrupts from the means for storing a plurality of interrupt vectors to the means for comparing.

Claim 6

A programmable interrupt controller according to claim 4, further comprising: register means for storing a state of the sequencer means and storing a prevailing interrupt source; and a control logic unit means for controlling a loading of the register means for storing a state of the sequencer means.

Claim 7

A programmable interrupt controller according to claim 1, wherein the means for storing a highest priority vector in service comprises: a register means accessible by a microprocessor, wherein when the microprocessor is executing a first interrupt routine from the programmable interrupt controller and a first interrupt vector is stored in the register means of the means for storing a highest priority vector in service, and the microprocessor is instructed to perform a higher priority interrupt routine, the microprocessor writes a higher priority interrupt vector into the register means of the means for storing a highest priority vector in service.

Claim 8

A programmable interrupt controller according to claim 6, wherein: the register means of the means for storing a highest priority vector in service is accessible by the microprocessor such that when the microprocessor is finished executing the higher priority interrupt routine, the microprocessor writes the first interrupt vector into the register means of the means for storing a highest priority vector in service, thereby giving the programmable interrupt controller a priority of the first interrupt vector, and the microprocessor resumes processing the first interrupt routine.

Claim 9

An apparatus according to claim 1, further comprising: means for writing an interrupt vector, corresponding to the received signal, in the means for storing a highest priority vector in service when the determining means determines that said received signal indicates a higher priority than the priority of said highest priority vector in service.

Claim 10

A programmable interrupt controller according to claim 1, wherein: the internal bus comprises a transmitting bus and a receiving bus; and the interface means comprises: an output buffer means, connected between the transmitting bus and the external bus, which selectively allows transmission of bits of the vector stored in the means for storing a highest priority vector in service; and an input buffer connected between the outer bus and the external bus.

Claim 11

A programmable interrupt controller according to claim 9, wherein the determining means comprises: a comparator circuit means for each bit of the vector stored in the means for storing the highest priority in service, each of the comparator circuit means compares a bit of the highest priority vector in service with a corresponding bit of the received signal and outputs an indication of whether said bit has a higher priority than a priority of the corresponding bit of the received signal.

Claim 12

A programmable interrupt controller according to claim 10, further comprising: a plurality of resistors, each connected to a corresponding bit line of the external bus, which places a lower priority signal on the corresponding bit line when the higher priority signal is absent from the bit line.

Claim 13

A programmable interrupt controller according to claim 1, further comprising: a plurality of resistors, each connected to a corresponding bit line of the external bus, which places a lower priority signal on the corresponding bit line when the higher priority signal is absent from the bit line.

Claim 14

A programmable interrupt controller according to claim 1, wherein: the external bus is a data bus.

Claim 15

A microprocessor interrupt system, comprising: a plurality of interrupt controllers, each interrupt controller comprising: interrupt request register means, connected to a plurality of interrupt sources through a plurality of interrupt lines, for storing interrupt requests from the interrupt sources; interrupt mask register means, connected to the internal bus, for programmably masking interrupt levels; means for storing a plurality of interrupt vectors, connected to the internal bus, each stored interrupt vector having an interrupt priority and corresponding to one of the interrupt sources; means for storing a highest priority vector in service, connected to the internal bus; means for comparing, connected to the internal bus, the priorities, which are stored in said means for storing a plurality of interrupt vectors, of active and non-masked interrupt vectors and the highest priority vector in service to determine a highest priority vector and loading said means for storing a highest priority vector in service with the determined highest priority vector; interface means, connected to the internal bus and an external bus, for transmitting the vector stored in the means for storing a highest priority vector in service to the external bus and for simultaneously receiving a signal having a priority which is present on the external bus, said received signal being a combination of said vector transmitted by the interface means and vectors transmitted by interface means of others of said plurality of interrupt controllers; and determining means, connected to the interface means, for determining if said highest priority vector in service has a higher priority than the priority of the received signal which is present on the external bus.

Claim 16

A microprocessor interrupt system, comprising: a plurality of interrupt controllers, each interrupt controller comprising: interrupt request register means, connected to a plurality of interrupt sources through a plurality of interrupt lines, for storing interrupt requests from the interrupt sources; interrupt mask register means, connected to the internal bus, for programmably masking interrupt levels; means for storing a plurality of interrupt vectors, connected to the internal bus, each stored interrupt vector having an interrupt priority and corresponding to one of the interrupt sources; means for storing a highest priority vector in service, connected to the internal bus; means for comparing, connected to the internal bus, the priorities, which are stored in said means for storing a plurality of interrupt vectors, of active and non-masked interrupt vectors and the highest priority vector in service to determine a highest priority vector and loading said means for storing a highest priority vector in service with the determined highest priority vector; interface means, connected to the internal bus and an external bus, for transmitting the vector stored in the means for storing a highest priority vector in service to the external bus and for simultaneously receiving a signal having a priority which is present on the external bus, said received signal being a combination of said vector transmitted by the interface means and vectors transmitted by interface means of others of said plurality of interrupt controllers; and determining means, connected to the interface means, for determining if said highest priority vector in service has a higher priority than the priority of the received signal which is present on the external bus.

Claim 17

An interrupt system according to claim 14, wherein each of said plurality of interrupt controllers has an equal control of said microprocessor interrupt system.

Claim 20

A method according to claim 16, further comprising the step of: validating a transmission on the data bus of a predetermined weight bit of the highest priority vector in service when an one higher weight bit then the predetermined weight bit of the highest priority vector in service is equivalent to an one higher weight bit then the predetermined weight bit a of input data.

Claim 21

A method according to claim 16, further comprising the step: validating the transmission of a bit of the highest priority vector in service only if the bit is in a dominant state and not validating the transmission if the bit is in a recessive state.

Claim 22

A programmable interrupt controller according to claim 16, wherein: the external bus is a data bus.

Claim 23

A programmable interrupt controller for a microprocessor interrupt system for use with a microprocessor, comprising: a control logic circuit unit for controlling a transmission of an interrupt request to the microprocessor and for receiving interrupt authorization from the microprocessor; interrupt request register means, connected to a plurality of interrupt sources through a plurality of interrupt lines, for storing interrupt requests from the interrupt sources; interrupt mask register means, connected to an internal data bus, for programmably masking interrupt levels; means for storing a plurality of interrupt vectors, connected to the internal data bus, each stored interrupt vector defining an interrupt priority and corresponding to one of the interrupt sources; storing means for storing a highest priority vector in service, connected to the internal data bus; means for comparing, connected to the internal data bus, each active and non-masked interrupt vector of said stored interrupt vectors with the vector stored in the storing means for storing a highest priority vector in service in order to determine a new highest priority vector and loading said new highest priority vector in the said storing means for storing a highest priority vector; and a send/receive unit including: interface means for receiving data present on an external bus and transmitting said data received from the external bus to the internal data bus; contention means for comparing the data of the internal bus with the highest priority vector stored in the storing means and for determining a new highest priority vector and transmitting the new highest priority vector to the external bus via the interface means.

Claim 24

A programmable interrupt controller for a microprocessor interrupt system for use with a microprocessor, comprising: a control logic circuit unit for controlling a transmission of an interrupt request to the microprocessor and for receiving interrupt authorization from the microprocessor; interrupt request register means, connected to a plurality of interrupt sources through a plurality of interrupt lines, for storing interrupt requests from the interrupt sources; interrupt mask register means, connected to an internal data bus, for programmably masking interrupt levels; means for storing a plurality of interrupt vectors, connected to the internal data bus, each stored interrupt vector defining an interrupt priority and corresponding to one of the interrupt sources; storing means for storing a highest priority vector in service, connected to the internal data bus; means for comparing, connected to the internal data bus, each active and non-masked interrupt vector of said stored interrupt vectors with the vector stored in the storing means for storing a highest priority vector in service in order to determine a new highest priority vector and loading said new highest priority vector in the said storing means for storing a highest priority vector; and a send/receive unit including: interface means for receiving data present on an external bus and transmitting said data received from the external bus to the internal data bus; contention means for comparing the data of the internal bus with the highest priority vector stored in the storing means and for determining a new highest priority vector and transmitting the new highest priority vector to the external bus via the interface means.

Claim 25

A programmable interrupt controller according to claim 20, wherein the contention means comprises: means for validating a transmission, by the interface means, to the external data bus, of a predetermined weight bit of the highest priority vector stored in the storing means for storing a highest priority vector in service, only if there is equivalence between a bit, one higher in weight then the predetermined weight bit of the highest priority vector in service and a bit, one higher in weight then the predetermined weight bit, of input data from the internal data bus.

Claim 26

A programmable interrupt controller according to claim 20, wherein the interface means comprises: means for validating transmission of a bit of the highest priority vector in service to the external data bus if the bit is in a dominant state and for not validating the transmission if the bit is in a recessive state.

Claim 27

A programmable interrupt controller according to claim 20, wherein the control logic unit assures the acknowledgement of said interrupt request register means validates a transmission contention of the prevailing vector by said send/receive unit, and controls a loading of the prevailing vector in the storing means for storing a highest priority vector.

Claim 28

A programmable interrupt controller according to claim 20, further comprising: sequencer means, connected to the internal bus means, for sequentially sending active and non-masked interrupts from the means for storing a plurality of interrupt vectors to the means for comparing.

Claim 29

A programmable interrupt controller according to claim 24, further comprising: register means for storing a state of the sequencer means and storing a prevailing interrupt source; and a control logic unit means for controlling a loading of the register means for storing a state of the sequencer means.

Claim 30

A programmable interrupt controller according to claim 20, wherein the means for storing a highest priority vector in service comprises: a register means accessible by a microprocessor, wherein when the microprocessor is executing a first interrupt routine from the programmable interrupt controller and a first interrupt vector is stored in the register means of the means for storing a highest priority vector in service, and the microprocessor is instructed to perform a higher priority interrupt routine, the microprocessor writes a higher priority interrupt vector into the register means of the means for storing a highest priority vector in service.

Claim 31

A programmable interrupt controller according to claim 26, wherein: the register means of the means for storing a highest priority vector in service is accessible by the microprocessor such that when the microprocessor is finished executing the higher priority interrupt routine, the microprocessor writes the first interrupt vector into the register means of the means for storing a highest priority vector in service, thereby giving the programmable interrupt controller a priority of the first interrupt vector, and the microprocessor resumes processing the first interrupt routine.

Claim 32

An apparatus according to claim 20, further comprising: means for writing an interrupt vector, corresponding to the received signal, in the means for storing a highest priority vector in service when the contention means determines that said received data indicates a higher priority than the priority of said highest priority vector in service.

Claim 33

A programmable interrupt controller according to claim 20, wherein the interface means comprises: an output buffer means, connected between the transmitting data bus and the external data bus means, which selectively allows transmission of bits of the vector stored in the means for storing a highest priority vector in service; and an input buffer connected between the outer bus and the internal data bus.

Claim 34

A programmable interrupt controller according to claim 29, wherein the contention means comprises: a comparator circuit means for each bit of the vector stored in the means for storing the highest priority in service, each of the comparator circuit means compares a bit of the highest priority vector in service with a corresponding bit of the received data on the internal data bus and outputs an indication of whether said bit has a higher priority than a priority of the corresponding bit of the received data.

Claim 35

A programmable interrupt controller according to claim 30, wherein the comparator circuit means comprises a plurality of gates that each receives a bit of the prevailing vector as the corresponding bit present on the internal data bus.

Claim 36

A programmable interrupt controller according to claim 20, further comprising: a plurality of resistors, each connected to a corresponding bit line of the external bus means, places a lower priority signal on the corresponding bit line when the higher priority signal is absent from the bit line.

Claim 37

A microprocessor interrupt system, comprising: a plurality of interrupt controllers, each interrupt controller comprising: a control logic circuit unit for controlling a transmission of an interrupt request to the microprocessor and for receiving interrupt authorization from the microprocessor; interrupt request register means, connected to a plurality of interrupt sources through plurality of interrupt lines, for storing interrupt requests from the interrupt sources; interrupt mask register means, connected to an internal data bus, for programmably masking interrupt levels; means for storing a plurality of interrupt vectors, connected to the internal data bus, each stored interrupt vector defining an interrupt priority and corresponding to one of the interrupt sources; storing means for storing a highest priority vector in service, connected to the internal data bus; means for comparing, connected to the internal data bus, each active and non-masked interrupt vector of said stored interrupt vectors with the vector stored in the storing means for storing a highest priority vector in service in order to determine a new highest priority vector and loading said new highest priority vector in the said storing means for storing a highest priority vector; and a send/receive unit including: interface means for receiving data present on an external bus and transmitting said data received from the external bus to the internal data bus; contention means for comparing the data of the internal bus with the highest priority vector stored in the storing means and for determining a new highest priority vector and transmitting the new highest priority vector to the external bus via the interface means.

Claim 38

A microprocessor interrupt system, comprising: a plurality of interrupt controllers, each interrupt controller comprising: a control logic circuit unit for controlling a transmission of an interrupt request to the microprocessor and for receiving interrupt authorization from the microprocessor; interrupt request register means, connected to a plurality of interrupt sources through plurality of interrupt lines, for storing interrupt requests from the interrupt sources; interrupt mask register means, connected to an internal data bus, for programmably masking interrupt levels; means for storing a plurality of interrupt vectors, connected to the internal data bus, each stored interrupt vector defining an interrupt priority and corresponding to one of the interrupt sources; storing means for storing a highest priority vector in service, connected to the internal data bus; means for comparing, connected to the internal data bus, each active and non-masked interrupt vector of said stored interrupt vectors with the vector stored in the storing means for storing a highest priority vector in service in order to determine a new highest priority vector and loading said new highest priority vector in the said storing means for storing a highest priority vector; and a send/receive unit including: interface means for receiving data present on an external bus and transmitting said data received from the external bus to the internal data bus; contention means for comparing the data of the internal bus with the highest priority vector stored in the storing means and for determining a new highest priority vector and transmitting the new highest priority vector to the external bus via the interface means.

Claim 41

A method according to claim 34, further comprising the step of: validating a transmission on the data bus of a predetermined weight bit of the highest priority vector in service when an one higher weight bit then the predetermined weight bit of the highest priority vector in service is equivalent to an one higher weight bit then the predetermined weight bit a of input data.

Claim 42

A method according to claim 34, further comprising the step: validating the transmission of a bit of the highest priority vector in service only if the bit is in a dominant state and not validating the transmission if the bit is in a recessive state.