Apparatus for controlling I/O interrupt in multiprocessor system

Claim 1

In a multiprocessor system comprising a plurality of instruction processors, a system controller to which said instruction processors are connected, a shared main storage which is connected to said system controller and which stores pending interrupt requests in the form of a queue for each of a plurality of levels of interrupt, and a channel controller connected to said system controller, an apparatus for controlling interrupts which is provided in said system controller and which enables said instruction processors to process interrupt requests from said channel controller, said apparatus comprising: register means provided with a plurality of memory positions corresponding to the respective levels of interrupt queues, said memory positions being set when an interrupt request is received having the corresponding level and which indicates whether the corresponding queue is empty or not empty; a plurality of interrupt control means each provided for a respective one of said instruction processors, each of said interrupt control means including: (a) holding means for holding interrupt control data which indicates the ability of the corresponding instruction processor to process each of the plurality of levels of interrupt, and (b) output means responsive to the contents of said register means and the contents of said holding means for generating an interrupt selection request signal indicating the existence of an interrupt request which the corresponding instruction processor is able to process for selecting the interrupt queue of an interrupt which is to be processed, and for outputting a selected queue-identifier signal which identifies the selected interrupt queue to the corresponding instruction processor; comparator means for comparing the queue-identifier signals from said plurality of output means and for outputting a coincidence/noncoincidence signal indicating the result of said comparison; and selection means connected to each of said interrupt control means and to said comparator means for applying an interrupt processing instruction signal to said instruction processors in response to said interrupt selection request signals and said coincidence/noncoincidence signals so that one instruction processor is selected for each selected interrupt queue in response to interrupt selection request signals from said plurality of output means and said coincidence/noncoincidence signals from said comparator means.