US4755938A — Access request control apparatus which reassigns …

Claim 1

Independent Claim 310 words

An access request control apparatus for a pipeline control system connected to a memory apparatus and access request apparatuses including channel processing apparatuses (CHP's) and central processing units (CPU's) which together comprise a data processing system, said access request control apparatus processing channel and central access requests from the channel processing apparatuses and central processing units, respectively, to the memory apparatus, said access request control apparatus comprising: accepting means, connected to the access request apparatuses, for accepting the access requests from the access request apparatuses; determining means, connected to said accepting means, for determining priority of access requests which are simultaneously accepted from the plurality of access request apparatuses; selection means, connected to said accepting means and said determining means, for selecting a selected channel access request in dependence upon the priority determined by said determining means from among the channel access requests accepted by said accepting means, and for selecting a selected access request from among the selected channel access request and the central access requests accepted by said accepting means with the selected channel access request assigned a first priority higher than a second priority assigned to the central access requests; processing start means, connected to said selecting means and the pipeline control system, for starting processing of the selected access request; nullification means, connected to the pipeline control system and said determining means, nullifying the selected access request if the processing of the selected access request cannot be completed, thereby producing a nullified access request; and return means, connected to the pipeline control system, said nullification means and said processing start means, for returning the nullified access request to said determining means via said accepting means, said determining means thereafter determining priority again, during which a third priority higher than the first priority is assigned to the nullified access request for competition with the accepted access requests.

Claim 2

Dependent Claim 310 words

An access request control apparatus for a pipeline control system connected to a memory apparatus and access request apparatuses including channel processing apparatuses (CHP's) and central processing units (CPU's) which together comprise a data processing system, said access request control apparatus processing channel and central access requests from the channel processing apparatuses and central processing units, respectively, to the memory apparatus, said access request control apparatus comprising: accepting means, connected to the access request apparatuses, for accepting the access requests from the access request apparatuses; determining means, connected to said accepting means, for determining priority of access requests which are simultaneously accepted from the plurality of access request apparatuses; selection means, connected to said accepting means and said determining means, for selecting a selected channel access request in dependence upon the priority determined by said determining means from among the channel access requests accepted by said accepting means, and for selecting a selected access request from among the selected channel access request and the central access requests accepted by said accepting means with the selected channel access request assigned a first priority higher than a second priority assigned to the central access requests; processing start means, connected to said selecting means and the pipeline control system, for starting processing of the selected access request; nullification means, connected to the pipeline control system and said determining means, nullifying the selected access request if the processing of the selected access request cannot be completed, thereby producing a nullified access request; and return means, connected to the pipeline control system, said nullification means and said processing start means, for returning the nullified access request to said determining means via said accepting means, said determining means thereafter determining priority again, during which a third priority higher than the first priority is assigned to the nullified access request for competition with the accepted access requests.

Claim 3

Dependent Claim 220 words

An access request control apparatus according to claim 1, wherein said accepting means receives CPU access requests from the CPU's and CHP access requests from the CHP's, wherein said return means comprises a loop-back circuit, connected to the pipeline control system and said accepting means, for routing a loop-back (LB) access request from the pipeline control system to said accepting means, and wherein said selection means comprises a first priority determination circuit, connected to said accepting means, for selecting a selected CHP access request from among two or more of the CHP access requests; and a second priority determination circuit, connected to the pipeline control system, said loop-back circuit, said accepting means and said first priority determination circuit, having a CPU flag bit for selecting from among the selected CHP access request, the CPU access requests and the LB access request, assigning to the selected CHP access request a higher priority than that of the CPU access requests, and, when the CPU access requests compete, assigning the priority to the CPU access requests in accordance with the flag bit's indication of priority between the CPU access requests, and assigning the LB access request a highest priority, the selected CHP access request, if not selected by said second priority determination circuit, retaining the higher priority in said first priority determination circuit.

Claim 4

Dependent Claim 249 words

An access request control apparatus for a pipeline control system connected to a memory apparatus and access request apparatuses including channel processing apparatuses (CHP's) and central processing units (CPU's) which together comprise a data processing system, said access request control apparatus processing access requests from the access request apparatuses to the memory apparatus and comprising: accepting means for receiving CPU access requests from he CPU's and CHP access requests from the CHP's; a loop-back circuit, connected to the pipeline control system and said accepting means, for routing a loop-back (LB) access request from the pipeline control system to said accepting means; a first priority determination circuit, connected to said accepting means, for selecting a selected CHP access request from among two or more of the CHP access requests; and a second priority determination circuit, connected to the pipeline control system, said loop-back circuit, said accepting means and said first priority determination circuit, having a CPU flag bit, for selecting from among the selected CHP access request, the CPU access requests and the LB access request, assigning to the selected CHP access request a higher priority than that of the CPU access requests, and, when the CPU access requests compete, assigning the higher priority in accordance with the flag bit's indication of priority between CPU access requests, and assigning to the LB access request a highest priority, the selected CHP access request, if not selected by said second priority determination circuit, retaining the higher priority in said priority determination circuit.

Claim 5

Dependent Claim 249 words

An access request control apparatus for a pipeline control system connected to a memory apparatus and access request apparatuses including channel processing apparatuses (CHP's) and central processing units (CPU's) which together comprise a data processing system, said access request control apparatus processing access requests from the access request apparatuses to the memory apparatus and comprising: accepting means for receiving CPU access requests from he CPU's and CHP access requests from the CHP's; a loop-back circuit, connected to the pipeline control system and said accepting means, for routing a loop-back (LB) access request from the pipeline control system to said accepting means; a first priority determination circuit, connected to said accepting means, for selecting a selected CHP access request from among two or more of the CHP access requests; and a second priority determination circuit, connected to the pipeline control system, said loop-back circuit, said accepting means and said first priority determination circuit, having a CPU flag bit, for selecting from among the selected CHP access request, the CPU access requests and the LB access request, assigning to the selected CHP access request a higher priority than that of the CPU access requests, and, when the CPU access requests compete, assigning the higher priority in accordance with the flag bit's indication of priority between CPU access requests, and assigning to the LB access request a highest priority, the selected CHP access request, if not selected by said second priority determination circuit, retaining the higher priority in said priority determination circuit.

Claim 6

Dependent Claim 57 words

An access request control apparatus according to claim 3, wherein each of the CHP's have a state, and wherein said first priority determination circuit comprises a state indication register, connected to said accepting means, indicating the state of each of the CHP's, and said first priority determination circuit determines priority based on said state indication register's contents.

Claim 7

Dependent Claim 281 words

An access request control apparatus for a pipeline control system connected to a memory apparatus and access request apparatuses including channel processing apparatus (CHP's) and central processing units (CPU's) which together comprise a data processing system, the CHP's generating CHP access requests and CPU's generating CPU access requests having different kinds of operations, said access request control apparatus processing the access requests from the access request apparatuses to the memory apparatus by applying a priority determination formula, said access request control apparatus comprising: a loop-back circuit, connected to the pipeline control system, for receiving loop back (LB) access requests which require processing through the pipeline control system more than once; a first priority determination circuit, connected to the CHP's, for selecting a selected CHP access request from among two or more CHP access requests; and a second priority determination circuit, connected to the CPU's, said loop-back circuit and said first priority determination circuit, for selecting from among the selected CHP access request, the CPU access requests and the LB access requests, said second priority determination circuit having a flag bit indicating priority between the CPU access requests, assigning to the selected CHP access request a first priority which is higher than that of the CPU access requests, assigning a second priority to the CPU access requests in accordance with the flag bit's indication of priority between the CPU access requests when the CPU access requests compete, and assigning to the LB access requests a third priority higher than that of the first and second priorities, said priority determination formula being modified in said second priority determination circuit in accordance with the kind of operation the CPU access requests are to perform.

Claim 8

Dependent Claim 281 words

An access request control apparatus for a pipeline control system connected to a memory apparatus and access request apparatuses including channel processing apparatus (CHP's) and central processing units (CPU's) which together comprise a data processing system, the CHP's generating CHP access requests and CPU's generating CPU access requests having different kinds of operations, said access request control apparatus processing the access requests from the access request apparatuses to the memory apparatus by applying a priority determination formula, said access request control apparatus comprising: a loop-back circuit, connected to the pipeline control system, for receiving loop back (LB) access requests which require processing through the pipeline control system more than once; a first priority determination circuit, connected to the CHP's, for selecting a selected CHP access request from among two or more CHP access requests; and a second priority determination circuit, connected to the CPU's, said loop-back circuit and said first priority determination circuit, for selecting from among the selected CHP access request, the CPU access requests and the LB access requests, said second priority determination circuit having a flag bit indicating priority between the CPU access requests, assigning to the selected CHP access request a first priority which is higher than that of the CPU access requests, assigning a second priority to the CPU access requests in accordance with the flag bit's indication of priority between the CPU access requests when the CPU access requests compete, and assigning to the LB access requests a third priority higher than that of the first and second priorities, said priority determination formula being modified in said second priority determination circuit in accordance with the kind of operation the CPU access requests are to perform.

Claim 9

Dependent Claim 99 words

An access request control apparatus according to claim 5, wherein the CPU access requests include an n-byte access request and a block access request in which a first n-byte access request is carried out and then repeated for a second and successive times, where n is an integer larger than 1, and wherein said second priority determination circuit assigns a fourth priority to the second and successive n-byte access requests of the block access request which is higher than the second priority assigned to the n-byte access request and the first n-byte access request of the block access request.

Claim 10

Dependent Claim 99 words

An access request control apparatus according to claim 6, wherein said second priority determination circuit further comprises block access flags, each corresponding to one of the central processing units, and wherein when said second priority determination circuit selects a selected block access request and begins processing the first n-byte access request of the selected block access request, the block access flag corresponding to the central processing unit from which said selected block access request was sent, is turned ON, indicating that the second and successive n-byte access requests of said selected block access request will receive the fourth priority.

Claim 11

Dependent Claim 196 words

An access request control device in a data processing system which includes a memory unit and access request devices which send access requests to said access request control device requesting access to the memory unit, said access request control device comprising: priority control means, connected to the access request devices, for processing control of the access requests by assigning priority to access requests during acceptance by said access request control device; selection means, connected to the access request devices and said priority control means, for selecting a selected access request from among the access requests accepted by said access request control device in dependence upon the priority assigned thereto and issuing the selected access request for processing; nullification means, connected to said selection means via said priority control means, for nullifying the selected access request, if the selected access request cannot be fully processed, and then reassigning higher priority to access requests which have been nullified; and access request pipeline processing means, connected to the memory unit, said priority control means, said selection means and said nullification means, for processing the selected access requests and returning access requests which have been nullified to said selection means.

Claim 12

Dependent Claim 196 words

An access request control device in a data processing system which includes a memory unit and access request devices which send access requests to said access request control device requesting access to the memory unit, said access request control device comprising: priority control means, connected to the access request devices, for processing control of the access requests by assigning priority to access requests during acceptance by said access request control device; selection means, connected to the access request devices and said priority control means, for selecting a selected access request from among the access requests accepted by said access request control device in dependence upon the priority assigned thereto and issuing the selected access request for processing; nullification means, connected to said selection means via said priority control means, for nullifying the selected access request, if the selected access request cannot be fully processed, and then reassigning higher priority to access requests which have been nullified; and access request pipeline processing means, connected to the memory unit, said priority control means, said selection means and said nullification means, for processing the selected access requests and returning access requests which have been nullified to said selection means.

Claim 13

Dependent Claim 326 words

An access request control device in a data processing system which includes a memory unit and access request devices, divided into a first access request group and a second access request group, which send access requests to said access request control device requesting access to the memory unit, said access request control device comprising: access request pipeline processing means, connected to the memory unit, for processing the selected access requests, said access request pipeline processing means having an entrance and an exit, incompletely processed access requests being returned from the exit towards the entrance for reexecution; first priority determination means, connected to the first access request group, for accepting one of the access requests at a time from each of the access request devices in the first access request group, selecting a first selected access request from among the access requests accepted from the first access request group and assigned a first priority to the first selected access request; second priority determination means, connected to the second access request group, said first priority determination means and said access request pipeline processing means, for accepting one access request at a time from each of the access request devices in the second access request group, assigning a second priority to access requests accepted from the second access request group, assigning a third priority, different from the first and second priorities, to the incompletely processed access requests returned by said access request pipeline processing means, selecting a second selected access request from among the first selected access request, the access requests accepted from the second access request group and the incompletely processed access requests, and issuing said second selected access request to the entrance of said access request pipeline processing means for processing; and nullification control means, connected to said access request pipeline processing means and said first priority determination means, for nullifying access requests in said access request pipeline processing means which are unable to be completely processed.

Claim 14

Dependent Claim 326 words

An access request control device in a data processing system which includes a memory unit and access request devices, divided into a first access request group and a second access request group, which send access requests to said access request control device requesting access to the memory unit, said access request control device comprising: access request pipeline processing means, connected to the memory unit, for processing the selected access requests, said access request pipeline processing means having an entrance and an exit, incompletely processed access requests being returned from the exit towards the entrance for reexecution; first priority determination means, connected to the first access request group, for accepting one of the access requests at a time from each of the access request devices in the first access request group, selecting a first selected access request from among the access requests accepted from the first access request group and assigned a first priority to the first selected access request; second priority determination means, connected to the second access request group, said first priority determination means and said access request pipeline processing means, for accepting one access request at a time from each of the access request devices in the second access request group, assigning a second priority to access requests accepted from the second access request group, assigning a third priority, different from the first and second priorities, to the incompletely processed access requests returned by said access request pipeline processing means, selecting a second selected access request from among the first selected access request, the access requests accepted from the second access request group and the incompletely processed access requests, and issuing said second selected access request to the entrance of said access request pipeline processing means for processing; and nullification control means, connected to said access request pipeline processing means and said first priority determination means, for nullifying access requests in said access request pipeline processing means which are unable to be completely processed.

Claim 15

Dependent Claim 67 words

An access request control device as set forth in claim 9, wherein said access request pipeline processing means comprises: pipeline stages connected to the memory unit, said second priority determination means and said nullification control means; and a loop-back circuit, connected to said second priority determination means and said pipeline stages, for returning access requests which have not been fully processed to said second priority determination means.

Claim 16

Dependent Claim 31 words

An access request control device as set forth in claim 9, wherein the first priority is higher than the second priority and the third priority is higher than the first priority.

Claim 17

Dependent Claim 47 words

An access request control device as set forth in claim 9, wherein, when said first priority determination means selects the first selected access request, the access requests which previously have been assigned the first priority are selected before the access requests which have not been assigned priority.

Claim 18

Dependent Claim 41 words

An access request control device as set forth in claim 9, wherein the access requests have different types of operations and the first, second and third priorities have priority levels which depend upon the type of operation of the access requests.

Claim 19

Dependent Claim 79 words

An access request control device as set forth in claim 13, wherein the access requests include byte access requests, and block access requests which require the processing of a first byte access request and second and successive byte access requests, and wherein said second priority determination means assigns a fourth priority to the second and successive access requests of the block access request, the fourth priority having a level greater than the levels of the first and second priorities.

Claim 20

Dependent Claim 68 words

An access request control device as set forth in claim 14, wherein the access requests include a pre-fetch access request which may require the processing of second and successive byte access requests, and wherein said second priority determination means assigns to the pre-fetch access request a fifth priority having a level lower than the level of the first priority and higher than the level of the second priority.

Claim 21

Independent Claim 170 words

A method for controlling access requests to a memory unit in a data processing system which includes first and second groups of access request devices generating access requests and an access request pipeline processing system, comprising the steps of: (a) accepting access requests in means for accepting the access requests simultaneously from the access request devices; (b) assigning priority in priority assigning means to access requests accepted in step (a); (c) selecting in selection means one access request from among the access requests accepted in step (a) based upon the priority assigned in step (b); (d) issuing from means for issuing the access request selected in step (c) to the access request pipeline processing system; (e) discriminating in discrimination means whether access requests exiting the access request pipeline processing system are incomplete access requests for which execution is incomplete; (f) reassigning in reassignment means a higher priority to the exiting incomplete access requests after said discriminating in step (e) discriminated the exiting incomplete access requests; and (g) repeating steps (a)-(f).

Claim 22

Independent Claim 170 words

A method for controlling access requests to a memory unit in a data processing system which includes first and second groups of access request devices generating access requests and an access request pipeline processing system, comprising the steps of: (a) accepting access requests in means for accepting the access requests simultaneously from the access request devices; (b) assigning priority in priority assigning means to access requests accepted in step (a); (c) selecting in selection means one access request from among the access requests accepted in step (a) based upon the priority assigned in step (b); (d) issuing from means for issuing the access request selected in step (c) to the access request pipeline processing system; (e) discriminating in discrimination means whether access requests exiting the access request pipeline processing system are incomplete access requests for which execution is incomplete; (f) reassigning in reassignment means a higher priority to the exiting incomplete access requests after said discriminating in step (e) discriminated the exiting incomplete access requests; and (g) repeating steps (a)-(f).

Claim 23

Dependent Claim 165 words

A method for controlling access requests as set forth in claim 16, wherein step (a) comprises the steps of: (ai) accepting first accepted access requests from the first group of access request devices; (aii) selecting a first selected access request from among the first accepted access requests and access requests from the first group of access request devices which were issued in step (d) but were not fully processed; and (aiii) accepting second accepted access requests from the second group of access request devices; wherein step (b) comprises the steps of: (bi) assigning a first priority to the first selected access request selected in step (aii); and (bii) assigning a second priority to the second accepted access requests accepted in step (aiii), wherein step (f) assigns a third priority to the access requests which have not been fully processed by the access request pipeline processing system, and wherein step (c) selects a second selected access request in dependence upon the first, second and third priorities.

Claim 24

Dependent Claim 69 words

A method for controlling requests in a data processing system as set forth in claim 17, wherein the first priority assigned in step (bi) has a level, the second priority assigned in step (bii) has a level which is lower than the level of the first priority and the third priority assigned in step (f) has a first level which is higher than the level of the first priority.

Claim 25

Dependent Claim 95 words

A method for controlling access requests in a data processing system as set forth in claim 18, wherein the access requests have different types of operations including a byte access request and a block access request having a first byte access and second and successive byte accesses, and wherein the byte access request and the first byte access of the block access request is assigned the second priority by step (bii) and the second and successive byte accesses of the block access request are assigned the first level of the third priority in step (f).

Claim 26

Dependent Claim 83 words

A method for processing access requests in a data processing system as set forth in claim 19, wherein the different types of operations of the access requests include a pre-fetch operation which may require second and successive byte accesses, and wherein the third priority assigned by step (f) has a second level, lower than the level of the first priority and higher than the level of the second priority, which is assigned to the second and successive byte accesses of the pre-fetch operation.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1991-07-05	1992-01-04	1992-07-05	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1995-07-05	1996-01-04	1996-07-05	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1999-07-05	2000-01-04	2000-07-05	$7700.00	Window Closed / Lapsed

Access request control apparatus which reassigns higher priority to incomplete access requests

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