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US5225358A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming late isolation with polishing

Assignee: LSI Corp
•
Filing: 1991-08-23
•
Granted: 1993-07-06
•
Expires: 2011-08-23
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Abstract

Abstract Isolation and passivation structures are formed in a single step, after transistor fabrication, by CVD deposition of a layer of oxide or BPSG over the wafer. The passivation/isolation layer overfills trenches formed for isolation and covers the patterned transistor device The layer is subsequently planarized by chem-mech polishing. With only one deposition step involved, to form both isolation structures and a passivation layer, there is significantly less strain on the thermal budget. Process and product by process are disclosed.

Inventors

  • 👤 Nicholas F. Pasch

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 19:31
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10P; H10P95/00; H10P95/06; H10P95/062; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/0147; H05; H05K; H05K1/00; H05K1/02; H05K1/11; H05K1/115; H05K3/00; H05K3/46; H05K3/4644; Y; Y10; Y10S; Y10S148/00; Y10S148/086

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 89 words
A method of forming isolated transistor structures in diffusion regions on a substrate, comprising in sequence: forming a trench in a substrate around a diffusion region; after forming the trench, forming a transistor structure in the diffusion region; and after forming the transistor structure, depositing an insulating layer onto the substrate, over-filling the trench and covering the diffusion region, thereby forming in a single step an isolation structure around the transistor structure and a passivation layer over the transistor structure, the isolation structure being integral with the passivation layer.
Claim 2
Independent Claim 89 words
A method of forming isolated transistor structures in diffusion regions on a substrate, comprising in sequence: forming a trench in a substrate around a diffusion region; after forming the trench, forming a transistor structure in the diffusion region; and after forming the transistor structure, depositing an insulating layer onto the substrate, over-filling the trench and covering the diffusion region, thereby forming in a single step an isolation structure around the transistor structure and a passivation layer over the transistor structure, the isolation structure being integral with the passivation layer.
Claim 3
Dependent Claim 12 words
A method according to claim 1, wherein: the insulating layer is oxide.
Claim 4
Dependent Claim 12 words
A method according to claim 1, wherein: the insulating layer is BPSG.
Claim 5
Dependent Claim 22 words
A method according to claim 1, further comprising; after depositing the insulation layer, polishing back the insulating layer until it is planar.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-07-05 1997-01-04 1997-07-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-07-05 2001-01-04 2001-07-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-07-05 2005-01-04 2005-07-06 $7700.00 Window Closed / Lapsed

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