Method of planarization of topologies in integrated circuit structures

Claim 1

A method of making a highly planarized integrated circuit structure having highly planarized oxide portions, without utilizing a planarizing layer of polysilicon nor a planarizing step where two different materials are simultaneously removed by the planarizing means, using a conformal layer of deposited oxide which is planarized to a predetermined level with respect to adjacent portions of the integrated circuit structure which comprises: (a) depositing said conformal oxide layer over said integrated circuit structure; (b) applying a patterned mask layer over said oxide layer with openings in registry with raised portions of said oxide layer; (c) etching said raised oxide portions down to approximately the same height as low portions of said oxide layer; (d) removing said mask layer; and (e) polishing the remaining portions of said oxide layer to obtain a highly planarized layer.

Claim 2

A method of making a highly planarized integrated circuit structure having highly planarized oxide portions, without utilizing a planarizing layer of polysilicon nor a planarizing step where two different materials are simultaneously removed by the planarizing means, using a conformal layer of deposited oxide which is planarized to a predetermined level with respect to adjacent portions of the integrated circuit structure which comprises: (a) depositing said conformal oxide layer over said integrated circuit structure; (b) applying a patterned mask layer over said oxide layer with openings in registry with raised portions of said oxide layer; (c) etching said raised oxide portions down to approximately the same height as low portions of said oxide layer; (d) removing said mask layer; and (e) polishing the remaining portions of said oxide layer to obtain a highly planarized layer.

Claim 3

A method of making a highly planarized integrated circuit structure having highly planarized oxide portions using deposited oxide which is planarized to a level adjacent portions of the integrated circuit structure which comprises: (a) depositing over an integrated circuit structure having first portions at a height higher than the remainder of said integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of said integrated circuit structure; (b) forming a patterned mask layer over said deposited oxide layer with openings therein in registry with said higher height first portions of said integrated circuit structure; (c) etching exposed portions of said conformal oxide layer through said mask openings down to a level approximately equal to the level of the unexposed portion of said conformal oxide layer; (d) removing said mask layer; and (e) polishing said oxide layer to remove raised portions of said conformal oxide layer remaining after said etching step to form a highly planarized structure.

Claim 4

A method of making a highly planarized integrated circuit structure having highly planarized oxide portions using deposited oxide which is planarized to a level adjacent portions of the integrated circuit structure which comprises: (a) depositing over an integrated circuit structure having first portions at a height higher than the remainder of said integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of said integrated circuit structure; (b) forming a patterned mask layer over said deposited oxide layer with openings therein in registry with said higher height first portions of said integrated circuit structure; (c) etching exposed portions of said conformal oxide layer through said mask openings down to a level approximately equal to the level of the unexposed portion of said conformal oxide layer; (d) removing said mask layer; and (e) polishing said oxide layer to remove raised portions of said conformal oxide layer remaining after said etching step to form a highly planarized structure.

Claim 19

A method of making a highly planarized integrated circuit structure having field oxide regions formed therein between active regions of a substrate, and at the same level as the active regions, which comprises: (a) patterning a silicon substrate with a first photoresist mask having openings therein conforming to desired formation of field oxide regions in said substrate between said active regions; (b) etching said silicon substrate through said photoresist mask to form openings in said substrate having a depth of from about 0.45 microns to about 0.55 microns; (c) removing said first photoresist mask; (d) depositing from about 7000 to about 9000 Angstroms of a conformal oxide layer over said substrate; (e) forming a second photoresist mask over said conformal oxide layer, said mask having openings therein in registry with the portions of said substrate between said openings etched in said substrate; (f) isotropically etching said conformal oxide layer through said second mask to a level substantially equal to the level of the masked portions of said conformal oxide layer; (g) removing said second photoresist mask; (h) polishing said conformal oxide layer to remove raised portions of said conformal oxide layer; and (i) anisotropically etching said conformal oxide layer to expose said active regions of said substrate to form a highly planarized structure having field oxide regions formed therein between said active regions in said substrate with the upper surface of said field oxide regions substantially level with the surface of said active regions.

Claim 20

A method of making a highly planarized integrated circuit structure having field oxide regions formed therein between active regions of a substrate, and at the same level as the active regions, which comprises: (a) patterning a silicon substrate with a first photoresist mask having openings therein conforming to desired formation of field oxide regions in said substrate between said active regions; (b) etching said silicon substrate through said photoresist mask to form openings in said substrate having a depth of from about 0.45 microns to about 0.55 microns; (c) removing said first photoresist mask; (d) depositing from about 7000 to about 9000 Angstroms of a conformal oxide layer over said substrate; (e) forming a second photoresist mask over said conformal oxide layer, said mask having openings therein in registry with the portions of said substrate between said openings etched in said substrate; (f) isotropically etching said conformal oxide layer through said second mask to a level substantially equal to the level of the masked portions of said conformal oxide layer; (g) removing said second photoresist mask; (h) polishing said conformal oxide layer to remove raised portions of said conformal oxide layer; and (i) anisotropically etching said conformal oxide layer to expose said active regions of said substrate to form a highly planarized structure having field oxide regions formed therein between said active regions in said substrate with the upper surface of said field oxide regions substantially level with the surface of said active regions.

Claim 22

A method of making a highly planarized integrated circuit structure having a raised pattern thereon, which comprises: (a) forming a raised pattern on an integrated circuit structure; (b) depositing, at a temperature which will not damage said raised pattern, a conformal oxide layer over said raised pattern having a thickness sufficient, at its lowest point, to exceed the height of said raised pattern; (c) forming a patterned mask layer over said conformal oxide layer, said mask having openings therein in registry with said raised pattern on said substrate; (d) isotropically etching said conformal oxide layer through said mask to a level substantially equal to the level of the masked portions of said conformal oxide layer; (e) removing said second mask; (f) polishing said conformal oxide layer to remove raised portions of said conformal oxide layer; and (g) anisotropically etching said conformal oxide layer to expose the upper surface of said raised pattern on said substrate to form a highly planarized structure having oxide regions formed therein between said raised pattern portions of said substrate with the upper surface of said oxide regions substantially level with the upper surface of said raised pattern.

Claim 23

A method of making a highly planarized integrated circuit structure having a raised pattern thereon, which comprises: (a) forming a raised pattern on an integrated circuit structure; (b) depositing, at a temperature which will not damage said raised pattern, a conformal oxide layer over said raised pattern having a thickness sufficient, at its lowest point, to exceed the height of said raised pattern; (c) forming a patterned mask layer over said conformal oxide layer, said mask having openings therein in registry with said raised pattern on said substrate; (d) isotropically etching said conformal oxide layer through said mask to a level substantially equal to the level of the masked portions of said conformal oxide layer; (e) removing said second mask; (f) polishing said conformal oxide layer to remove raised portions of said conformal oxide layer; and (g) anisotropically etching said conformal oxide layer to expose the upper surface of said raised pattern on said substrate to form a highly planarized structure having oxide regions formed therein between said raised pattern portions of said substrate with the upper surface of said oxide regions substantially level with the upper surface of said raised pattern.