Via-filling and planarization technique

Claim 1

A method of forming a plurality of conductive studs within an insulator layer disposed between a first series of conductive structures arranged on a substrate and a second series of conductive structures formed on an upper surface of the insulator layer, comprising the steps of: forming the insulator layer on the substrate, the insulator layer having a non-planar upper surface; defining vias through said non-planar upper surface of the insulator layer, so as to expose at least one of said plurality of first conductive structures disposed on the substrate; depositing a conductive layer on said non-planar upper surface of the insulator layer, said conductive layer completely filling said vias to contact said one of said plurality of first conductive structures, said conductive layer having a non-planar upper surface that substantially follows the topology of said non-planar upper surface of the insulating layer; and then subjecting both of said non-planar upper surface of said conductive layer and said non-planar upper surface of the insulator layer to a single polish etch step in the presence of an abrasive slurry, so as to remove portions of said conductive layer laying outside of said apertures in the insulator layer while simultaneously removing appreciable portions of said non-planar upper surface of the insulator layer so as to establish planarity in said upper surface of the insulator layer.

Claim 2

A method of forming a plurality of conductive studs within an insulator layer disposed between a first series of conductive structures arranged on a substrate and a second series of conductive structures formed on an upper surface of the insulator layer, comprising the steps of: forming the insulator layer on the substrate, the insulator layer having a non-planar upper surface; defining vias through said non-planar upper surface of the insulator layer, so as to expose at least one of said plurality of first conductive structures disposed on the substrate; depositing a conductive layer on said non-planar upper surface of the insulator layer, said conductive layer completely filling said vias to contact said one of said plurality of first conductive structures, said conductive layer having a non-planar upper surface that substantially follows the topology of said non-planar upper surface of the insulating layer; and then subjecting both of said non-planar upper surface of said conductive layer and said non-planar upper surface of the insulator layer to a single polish etch step in the presence of an abrasive slurry, so as to remove portions of said conductive layer laying outside of said apertures in the insulator layer while simultaneously removing appreciable portions of said non-planar upper surface of the insulator layer so as to establish planarity in said upper surface of the insulator layer.

Claim 11

A method of forming a plurality of conductive studs within a doped glass layer disposed between a first series of conductive structures arranged on a substrate and a second series of conductive structures formed on an upper surface of the passivation layer, comprising the steps of: depositing the doped glass layer on the substrate, the doped glass layer having a non-planar upper surface; defining vias in said non-planar upper surface of the doped glass layer, so as to expose one or more of said plurality of first conductive structures on said substrate, said vias having substantially vertical sidewalls; defining a conformal metal layer on said non-planar upper surface of the doped glass layer, said conformal metal layer filling said vias in the doped glass layer, said conformal metal layer having a non-planar upper surface that substantially follows the topology of said non-planar upper surface of the doped glass layer; subjecting both of said non-planar upper surface of said conformal metal layer and said non-planar upper surface of the doped glass layer to a single polish etch step in the presence of a basic abrasive slurry, so as to remove portions of the conformal metal layer outside of said vias in the doped glass layer while simultaneously removing appreciable portions of said non-planar upper surface of the insulator layer so as to establish planarity in said upper surface of the doped glass layer.

Claim 12

A method of forming a plurality of conductive studs within a doped glass layer disposed between a first series of conductive structures arranged on a substrate and a second series of conductive structures formed on an upper surface of the passivation layer, comprising the steps of: depositing the doped glass layer on the substrate, the doped glass layer having a non-planar upper surface; defining vias in said non-planar upper surface of the doped glass layer, so as to expose one or more of said plurality of first conductive structures on said substrate, said vias having substantially vertical sidewalls; defining a conformal metal layer on said non-planar upper surface of the doped glass layer, said conformal metal layer filling said vias in the doped glass layer, said conformal metal layer having a non-planar upper surface that substantially follows the topology of said non-planar upper surface of the doped glass layer; subjecting both of said non-planar upper surface of said conformal metal layer and said non-planar upper surface of the doped glass layer to a single polish etch step in the presence of a basic abrasive slurry, so as to remove portions of the conformal metal layer outside of said vias in the doped glass layer while simultaneously removing appreciable portions of said non-planar upper surface of the insulator layer so as to establish planarity in said upper surface of the doped glass layer.