US4931723A — Automatic test system having a "true tester-per-p…

Claim 1

Independent Claim 93 words

A method for operating a multichannel tester for an electronic circuit in which each channel operates independent of all other channels and has a test pin for contacting a test point of a unit under test and a pin memory circuit for storing instructions which determine a state of operation of said test pin, the method comprising cycling said pin memory circuit to a next address only when a new test instruction is required to change a state of operation of that channel independent of a state of operation of all other channels.

Claim 2

Independent Claim 93 words

A method for operating a multichannel tester for an electronic circuit in which each channel operates independent of all other channels and has a test pin for contacting a test point of a unit under test and a pin memory circuit for storing instructions which determine a state of operation of said test pin, the method comprising cycling said pin memory circuit to a next address only when a new test instruction is required to change a state of operation of that channel independent of a state of operation of all other channels.

Claim 3

Dependent Claim 25 words

The method of claim 1 wherein said state of operation includes: driving said pin with a predetermined signal; and receiving data from said test point.

Claim 4

Dependent Claim 23 words

The method of claim 2 further comprising generating a clock signal; cycling said memory circuit, when required, in synchronism with said clock signal.

Claim 5

Dependent Claim 26 words

The method of claim 3 further comprising generating a signal which starts a test sequence for all channels and stops said test sequence for all channels.

Claim 6

Dependent Claim 16 words

The method of claim 4 wherein said predetermined signal and said received data are digital signals.

Claim 7

Independent Claim 149 words

A method for operating a multichannel tester for an electronic circuit in which each channel operates independent of all other channels having in each channel a test pin for contacting a test point of a unit under test a pin memory circuit storing test instructions which determine a state of operation of said test pin, and a channel control circuit coupled between said test pin and an output of said pin memory circuit, the method comprising: programming a timer in said channel control circuit utilizing instructions appearing at said output of said pin memory circuit to time a desired interval between a present state of operation of said test pin and a next state of operation of said pin; cycling said pin memory circuit to a next address to a new test instruction for said next state of operation of said test pin at the termination of said interval.

Claim 8

Independent Claim 149 words

A method for operating a multichannel tester for an electronic circuit in which each channel operates independent of all other channels having in each channel a test pin for contacting a test point of a unit under test a pin memory circuit storing test instructions which determine a state of operation of said test pin, and a channel control circuit coupled between said test pin and an output of said pin memory circuit, the method comprising: programming a timer in said channel control circuit utilizing instructions appearing at said output of said pin memory circuit to time a desired interval between a present state of operation of said test pin and a next state of operation of said pin; cycling said pin memory circuit to a next address to a new test instruction for said next state of operation of said test pin at the termination of said interval.

Claim 9

Dependent Claim 25 words

The method of claim 6 wherein said state of operation includes: driving said pin with a predetermined signal; and receiving data from said test point.

Claim 10

Dependent Claim 45 words

The method of claim 7 wherein said pin is driven by a pin driver circuit, and further comprising the step of placing said pin driver circuit in a high impedance state when said channel control circuit is instructed to receive data from said test point.

Claim 11

Dependent Claim 25 words

The method of claim 6 wherein said memory is cycled in synchronism with a clock signal which is common to all channels of said tester.

Claim 12

Dependent Claim 18 words

The method of claim 9 wherein a decoder and pin controller operate in synchronism with said clock signal.

Claim 13

Dependent Claim 47 words

The circuit of claim 10 wherein a start/stop signal starts a test sequence consisting of a sequence of test instructions in said pin memory in synchronism with a synch signal and stops said test sequence in synchronism with said synch signal in all channels of said tester.

Claim 14

Independent Claim 92 words

A method for operating a multichannel tester for an electronic circuit in which each channel operates independent of all other channels and has a test pin for contacting a test point of a unit under test and a pin memory circuit for storing instructions which determine a state of operation of said test pin, the method comprising cycling said pin memory circuit to a next address when a new test instruction is required to change a state of operation of that channel independent of a state of operation of all other channels.

Claim 15

Independent Claim 92 words

A method for operating a multichannel tester for an electronic circuit in which each channel operates independent of all other channels and has a test pin for contacting a test point of a unit under test and a pin memory circuit for storing instructions which determine a state of operation of said test pin, the method comprising cycling said pin memory circuit to a next address when a new test instruction is required to change a state of operation of that channel independent of a state of operation of all other channels.

Claim 16

Independent Claim 81 words

A method for controlling the operation of a component or board test system having a central processor, a clock generator, and a plurality of operating channels; each of said operating channels including a channel controller, memory, and pin electronics; comprising the steps of: loading the respective memories of said channel with respective independent, instruction sets corresponding to respective predetermined coordinated test sequences; and implementing said independent instruction sets synchronously, whereby each of said channels operates independently of other of said channels.

Claim 17

Independent Claim 81 words

A method for controlling the operation of a component or board test system having a central processor, a clock generator, and a plurality of operating channels; each of said operating channels including a channel controller, memory, and pin electronics; comprising the steps of: loading the respective memories of said channel with respective independent, instruction sets corresponding to respective predetermined coordinated test sequences; and implementing said independent instruction sets synchronously, whereby each of said channels operates independently of other of said channels.

Claim 18

Dependent Claim 65 words

A method as in claim 13, wherein said implementing step comprises, with respect to each of said channels, the steps of: decoding an instruction sequence from at least one preselected address of the channel memory to obtain event and timing information; operating said pin electronics in accordance with said event and timing information; and repeating said decoding and operating steps until completion of the test.

Claim 19

Dependent Claim 85 words

A method as in claim 14, wherein said decoding step comprises the steps of: identifying a state change command to mark the start of said instruction sequence, wherein said event information is obtained from said state change command; and identifying a next consecutive state change command, wherein the end of said instruction sequence is the bit preceding said next consecutive state change command, and said timing information is at least in part determined as a function of the number of bits in said instruction sequence.

Claim 20

Dependent Claim 14 words

A method as in claim 15, wherein said state change command is context dependent.

Claim 21

Dependent Claim 31 words

A method as in claim 15, wherein said state change command is a predetermined number of bits in length and includes a flag bit in the lowest significant bit position thereof.

Claim 22

Dependent Claim 26 words

A method as in claim 15, wherein said timing information is determined also as a function of a holdoff commannd sequence occurring in said instruction sequence.

Claim 23

Dependent Claim 35 words

A method as in claim 18, wherein each holdoff command in said holdoff command sequence is a predetermined number of bits in length and includes a flag bit in the lowest significant bit position thereof.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1993-06-04	1993-12-04	1994-06-05	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1997-06-04	1997-12-04	1998-06-05	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2001-06-04	2001-12-04	2002-06-05	$7700.00	Window Closed / Lapsed

Automatic test system having a "true tester-per-pin" architecture

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