US4639919A
Expired / Lapsed
US
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Distributed pattern generator
Assignee: International Business Machines Corp
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Filing: 1983-12-19
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Granted: 1987-01-27
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Expires: 2003-12-19
Abstract
Abstract An array testing apparatus includes a plurality of pin pattern generators for individually generating serial bit sequences required at each pin of a device under test during the testing operation. The individual pin pattern generators receive starting addresses from one or more programmable controllers and each pin pattern generator then performs a subroutine to repeat basic patterns or combinations of basic patterns as necessary. Both the pin pattern generators and the programmable controllers may include loop logic for obtaining the desired repetition sequences.
Inventors
- 👤 Yi-Hua E. Chang
- 👤 Algirdas J. Gruodis
- 👤 Hans P. Muhlfeld, Jr.
- 👤 Charles W. Rodriguez
- 👤 Mark L. Shulman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 07:02
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921; G01R31/3193; G01R31/31935; G11C29/04; G11C29/08; G11C29/12; G11C29/36; G01R31/31926
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
241 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of test vectors to said array terminals with each said test vector including a plurality of bits each of which is applied to a respective one of said array terminals, each terminal receiving a serial pattern of bits as its respective portion of said sequence of vectors, said apparatus including a plurality of pattern generating means each for separately generating said pattern of bits for a respective one of said terminals, each said pattern generating means comprising pattern generator storage means for storing a plurality of basic pattern, and repetition control means for reading out said basic patterns, combinations of said basic patterns and sequences of said combinations of said basic patterns in order to obtain said serial pattern of bits, said repetition control means including address means for generating an address to said pattern generator storage means for reading out a pattern memory word stored at said address, said pattern memory word including at least one of said basic patterns and said pattern memory word further including control data for controlling the combinations and repetitions of basic patterns to be read out of said pattern generator storage means, and said repetition control means further comprising logic means responsive to said control data for controlling said address means to provide a desired sequence of addresses to said pattern generator storage means.
Claim 2
Independent Claim
241 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of test vectors to said array terminals with each said test vector including a plurality of bits each of which is applied to a respective one of said array terminals, each terminal receiving a serial pattern of bits as its respective portion of said sequence of vectors, said apparatus including a plurality of pattern generating means each for separately generating said pattern of bits for a respective one of said terminals, each said pattern generating means comprising pattern generator storage means for storing a plurality of basic pattern, and repetition control means for reading out said basic patterns, combinations of said basic patterns and sequences of said combinations of said basic patterns in order to obtain said serial pattern of bits, said repetition control means including address means for generating an address to said pattern generator storage means for reading out a pattern memory word stored at said address, said pattern memory word including at least one of said basic patterns and said pattern memory word further including control data for controlling the combinations and repetitions of basic patterns to be read out of said pattern generator storage means, and said repetition control means further comprising logic means responsive to said control data for controlling said address means to provide a desired sequence of addresses to said pattern generator storage means.
Claim 3
Independent Claim
193 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of test vectors to said array terminals with each said test vector including a plurality of bits each of which is applied to a respective one of said array terminals, each terminal receiving a serial pattern of bits as its respective portion of said sequence of vectors, said apparatus including a plurality of pattern generating means each for separately generating said pattern of bits for a respective one of said terminals, each said pattern generating means comprising pattern generator storage means for storing at least one basic pattern, and repetition control means for reading said basic pattern out of said pattern generator storage means a predetermined number of times to obtain said serial pattern of bits, said apparatus further comprising data output means responsive to the output of said pattern generator storage means for generating an output signal in N-bit parallel from representing said serial pattern of bits, and parallel-to-serial conversion means responsive to said N-bit parallel output signal for applying said serial bit pattern to a respective one of said array terminals.
Claim 4
Independent Claim
193 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of test vectors to said array terminals with each said test vector including a plurality of bits each of which is applied to a respective one of said array terminals, each terminal receiving a serial pattern of bits as its respective portion of said sequence of vectors, said apparatus including a plurality of pattern generating means each for separately generating said pattern of bits for a respective one of said terminals, each said pattern generating means comprising pattern generator storage means for storing at least one basic pattern, and repetition control means for reading said basic pattern out of said pattern generator storage means a predetermined number of times to obtain said serial pattern of bits, said apparatus further comprising data output means responsive to the output of said pattern generator storage means for generating an output signal in N-bit parallel from representing said serial pattern of bits, and parallel-to-serial conversion means responsive to said N-bit parallel output signal for applying said serial bit pattern to a respective one of said array terminals.
Claim 5
Dependent Claim
28 words
A testing apparatus as defined in claim 2, wherein N is a number less than the number of bits in the output from said pattern generator storage means.
Claim 6
Dependent Claim
88 words
A testing apparatus as defined in claim 2, wherein the response of said array is monitored by receiving response data from a portion of said plurality of pins and comparing said response data to expected data, each said pattern generating means including control latch means for providing an output indicating that its respective pattern generating means is to act as a receiver, said output means being responsive to said output from said control latch means for providing data from said pattern generator storage means as said expected data.
Claim 7
Independent Claim
346 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of testing vectors to said array terminals with each test vector including a plurality of bits each of which is applied to a respective one of said array terminals, each terminal receiving a serial pattern of bits as its respective portion of said sequence of vectors, and the response of said array being monitored by receiving response data from a portion of said plurality of pins and comparing said response data to expected data, said apparatus including: a plurality of pattern generating means, each responsive to a respective pattern generating program for separately generating said pattern of bits for a respective one of said terminals, each said pattern generating means comprising pattern generator storage means for storing at least one basic pattern, and repetition control means for reading said basic pattern out of said pattern generator storage means a predetermined number of times to obtain said serial pattern of bits, each said pattern generating means including control latch means for providing an output indicating that its respective pattern generating means is to act as a receiver; data output means responsive to the output of said pattern generator storage means for generating an output signal in N-bit parallel form representing said serial pattern of bits, said output means being responsive to said output from said control latch means for providing data from said pattern generator storage means as said expected data; and parallel-to-serial conversion means responsive to said N-bit parallel output signal for applying said serial bit pattern to a respective one of said array terminals; comparison means for receiving said response data, expected data and mask data and for providing error output data, wherein said response data and said expected data are compared with one another in accordance with mask data, said output means being responsive to said output signal from said control latch means for providing a portion of the output from said pattern generator storage means to said comparison means as said mask data.
Claim 8
Independent Claim
346 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of testing vectors to said array terminals with each test vector including a plurality of bits each of which is applied to a respective one of said array terminals, each terminal receiving a serial pattern of bits as its respective portion of said sequence of vectors, and the response of said array being monitored by receiving response data from a portion of said plurality of pins and comparing said response data to expected data, said apparatus including: a plurality of pattern generating means, each responsive to a respective pattern generating program for separately generating said pattern of bits for a respective one of said terminals, each said pattern generating means comprising pattern generator storage means for storing at least one basic pattern, and repetition control means for reading said basic pattern out of said pattern generator storage means a predetermined number of times to obtain said serial pattern of bits, each said pattern generating means including control latch means for providing an output indicating that its respective pattern generating means is to act as a receiver; data output means responsive to the output of said pattern generator storage means for generating an output signal in N-bit parallel form representing said serial pattern of bits, said output means being responsive to said output from said control latch means for providing data from said pattern generator storage means as said expected data; and parallel-to-serial conversion means responsive to said N-bit parallel output signal for applying said serial bit pattern to a respective one of said array terminals; comparison means for receiving said response data, expected data and mask data and for providing error output data, wherein said response data and said expected data are compared with one another in accordance with mask data, said output means being responsive to said output signal from said control latch means for providing a portion of the output from said pattern generator storage means to said comparison means as said mask data.
Claim 9
Dependent Claim
56 words
A testing apparatus as defined in claim 5, said comparison means further providing error data and an error flag signal when an error is detected between said response and expected data, said pattern generating means further comprising error memory means responsive to said error load output signal and said error data for storing said error data.
Claim 10
Dependent Claim
136 words
A testing apparatus as defined in claim 6, wherein said comparison means receives said response data in N-bit parallel form during successive periods of time and compares said response data to said expected data to generate a comparison signal during each of said successive periods of time, said comparison means including comparison storage means for storing at least two consecutive comparison signals, and each of said error data signals including at least two comparison signals, said error flag output signal being provided for a duration corresponding to a plurality of successive error data signals, said pattern generating means further including counter means for providing a count output indicating the portion of the error flag output in which an error was detected, said comparison storage means storing said counter means output together with the associated comparison signal.
Claim 11
Dependent Claim
50 words
A testing apparatus as defined in claim 7, further comprising means for generating program step signals indicating respective steps in said testing program, and error flag storage means for storing said error flag output signals together with a program step signal indicating the program step in which an error occurred.
Claim 12
Dependent Claim
44 words
A testing apparatus as claimed in claim 8, further comprising means for counting said error flag output signals and for providing its count output as an address to said error flag storage means for controlling the location at which said error flags are stored.
Claim 13
Dependent Claim
77 words
A testing apparatus as defined in claim 9, further comprising maximum error register means for storing a value indicating a maximum number of failed cycles during a test program, comparator means for comparing said maximum number value to the value in said counter and for providing an output when said counter value indicates that said maximum number of failed cycles has been reached, and means responsive to the output of said comparator for interrupting said testing operation.
Claim 14
Independent Claim
334 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of test vectors to said array terminals with each said test vector including a plurality of bits each of which is applied to a respective one of said array terminals, each terminal receiving a serial pattern of bits as its respective portion of said sequence of vectors, said apparatus including: a plurality of pattern generating means, each responsive to a respective pattern generating program for separately generating said pattern of bits for a respective one of said terminals, each said pattern generating means comprising pattern generator storage means for storing at least one basic pattern, and repetition control means for reading said basic pattern out of pattern geneator storage means a predetermined number of times to obtain said serial pattern of bits, said pattern generating means reading out said basic pattern from said pattern generator storage means a predetermined number of times by performing a subroutine in which a predetermined sequence of addresses are provided to said pattern generator storage means, each said subroutine commencing at a respective starting address; controller means for providing a sequence of said starting addresses to each said pattern generating means, said controller means comprising a controller memory for storing a plurality of words at respective addresses, each said word including repeat control data and pin address data, controller addressing means for providing addresses to said controller memory means for selectively reding said words out of said controllr memory means, controller logic means responsive to the repeat control data portion of each output from said controller memory means for controlling the sequence of addresses provided to said controller memory means from said controller addressing means, and pin address generator means responsive to said pin address data portion of each output word from said controller memory means and also responsive to output signal from said controller logic means for generating said starting addresses for each of said pattern generating means.
Claim 15
Independent Claim
334 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of test vectors to said array terminals with each said test vector including a plurality of bits each of which is applied to a respective one of said array terminals, each terminal receiving a serial pattern of bits as its respective portion of said sequence of vectors, said apparatus including: a plurality of pattern generating means, each responsive to a respective pattern generating program for separately generating said pattern of bits for a respective one of said terminals, each said pattern generating means comprising pattern generator storage means for storing at least one basic pattern, and repetition control means for reading said basic pattern out of pattern geneator storage means a predetermined number of times to obtain said serial pattern of bits, said pattern generating means reading out said basic pattern from said pattern generator storage means a predetermined number of times by performing a subroutine in which a predetermined sequence of addresses are provided to said pattern generator storage means, each said subroutine commencing at a respective starting address; controller means for providing a sequence of said starting addresses to each said pattern generating means, said controller means comprising a controller memory for storing a plurality of words at respective addresses, each said word including repeat control data and pin address data, controller addressing means for providing addresses to said controller memory means for selectively reding said words out of said controllr memory means, controller logic means responsive to the repeat control data portion of each output from said controller memory means for controlling the sequence of addresses provided to said controller memory means from said controller addressing means, and pin address generator means responsive to said pin address data portion of each output word from said controller memory means and also responsive to output signal from said controller logic means for generating said starting addresses for each of said pattern generating means.
Claim 16
Dependent Claim
57 words
A testing apparatus as defined in claim 11, wherein said controller logic means provides an output signal representing the present stage in a repetition sequence and said pin address generating means comprises arithmetic means for performing an arithmetic operation defined by said pin address data on data represented by said output signal from said controller logic means.
Claim 17
Dependent Claim
49 words
A testing apparatus as defined in claim 11, wherein said logic means responds to said control data portion output from said controller memory means for cycling said memory addresses through a plurality of loops, said controller logic means output signal representing the status of respective ones of said loops.
Claim 18
Dependent Claim
94 words
A pattern generator for use in a memory tester for testing a memory under test having a plurality of pins, said memory tester being of the type including a pattern generator for generating a sequence of patterns and means for connecting said patterns to said plurality of pins, said pattern generator comprising: a programmable controller for generating a first sequence of starting addresses; and a plurality of pin pattern generators each responsive to one starting address for each generating plurality of pattern portions for application to a respective one of said plurality of pins.
Claim 19
Dependent Claim
94 words
A pattern generator for use in a memory tester for testing a memory under test having a plurality of pins, said memory tester being of the type including a pattern generator for generating a sequence of patterns and means for connecting said patterns to said plurality of pins, said pattern generator comprising: a programmable controller for generating a first sequence of starting addresses; and a plurality of pin pattern generators each responsive to one starting address for each generating plurality of pattern portions for application to a respective one of said plurality of pins.
Claim 20
Dependent Claim
61 words
A pattern generator as defined in claim 14, wherein each of said pin pattern generators comprises: means for storing at least one basic bit pattern; means for storing control data representing repetition information; and means for reading said at least one basic bit pattern out of said means for storing a predetermined number of times in accordance with said repetition information.
Claim 21
Independent Claim
154 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of input test vectors to said array terminals and monitoring the response of said array, said apparatus including a plurality of pattern generating means each responsive to a respective pattern generating program for generating a sequence of test signals to be applied to a respective one of said array terminals, each pattern generating means including pattern generator storage means for storing pattern data and programmed means responsive to a respective program for generating its respective sequence of test signals, each said programmed means including program storage means for storing said pattern generating program, and means responsive to said pattern generating program for reading a desired sequence of data out of said pattern generator storage means, said pattern generator storage means and said program storage means comprising a single memory addressed by common address means.
Claim 22
Independent Claim
154 words
An apparatus for testing an array having a plurality of terminals, said apparatus testing said array by applying a sequence of input test vectors to said array terminals and monitoring the response of said array, said apparatus including a plurality of pattern generating means each responsive to a respective pattern generating program for generating a sequence of test signals to be applied to a respective one of said array terminals, each pattern generating means including pattern generator storage means for storing pattern data and programmed means responsive to a respective program for generating its respective sequence of test signals, each said programmed means including program storage means for storing said pattern generating program, and means responsive to said pattern generating program for reading a desired sequence of data out of said pattern generator storage means, said pattern generator storage means and said program storage means comprising a single memory addressed by common address means.
Claim 23
Dependent Claim
35 words
A testing apparatus as defined in claim 16, wherein said single address means comprises logic means responsive to program data read out of said program storage means for generating an address to said single memory.
Claim 24
Dependent Claim
57 words
A testing apparatus as defined in claim 16, wherein each said pattern generator storage means stores at least one basic pattern, and said programmed means is responsive to said respective pattern generating program for reading said basic pattern out of said pattern generator storage means a predetermined number of times to obtain said sequence of test signals.
Claim 25
Dependent Claim
52 words
A testing apparatus as defined in claim 18, wherein said pattern generator storage means stores a plurality of basic patterns and said programmed means reads out said basic patterns, combinations of said basic patterns and sequences of said combinations of said basic patterns in order to obtain said sequence of test signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-26 | 1990-07-28 | 1991-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-26 | 1994-07-28 | 1995-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-26 | 1998-07-28 | 1999-01-27 | $7700.00 | Window Closed / Lapsed |