US4493045A
Expired / Lapsed
US
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Test vector indexing method and apparatus
Assignee: National Semiconductor Corp
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Filing: 1981-10-19
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Granted: 1985-01-08
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Expires: 2001-10-19
Abstract
Abstract A data channel for a digital tester includes a random access local memory containing a main vector sequence, a subroutine vector sequence, and a test vector list. An index register is loaded with the address of the first vector in the list of vectors that is to be inserted as a variable into a vector stream. A sequence instruction selects the index register as the source of a test vector address when a variable vector is to be inserted into the vector stream at a point in a subroutine. The sequence instruction also resets the index register to a state which determines the address of the next variable to be inserted into the test vector pattern.
Inventors
- 👤 John H. Hughes, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 09:57
CPC Classifications
G; G01; G01R; G01R15/00; G01R15/12; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318371; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
132 words
A system for generating a sequence of test vectors, comprising: a first memory for storing a first set of test vectors and a second set of test vectors representing variables to be inserted in said first set of test vectors; a second memory for storing test pattern instructions; a test pattern controller responsive to the instructions stored in said second memory for addressing said first memory to access a test vector from said first set; a vector data controller responsive to the instructions stored in said second memory for addressing said first memory to access a test vector from said second set; and switching means for selectively applying address signals from said test pattern controller or said vector data controller to said first memory in accordance with instructions from said second memory.
Claim 2
Independent Claim
132 words
A system for generating a sequence of test vectors, comprising: a first memory for storing a first set of test vectors and a second set of test vectors representing variables to be inserted in said first set of test vectors; a second memory for storing test pattern instructions; a test pattern controller responsive to the instructions stored in said second memory for addressing said first memory to access a test vector from said first set; a vector data controller responsive to the instructions stored in said second memory for addressing said first memory to access a test vector from said second set; and switching means for selectively applying address signals from said test pattern controller or said vector data controller to said first memory in accordance with instructions from said second memory.
Claim 3
Dependent Claim
28 words
The system of claim 1 further including a third memory for storing synchronization information that is accessed in response to predetermined address signals from said test pattern controller.
Claim 4
Dependent Claim
34 words
The system of claim 1 wherein said vector data controller includes a register that is indexed to a predetermined location in response to an instruction from said second memory to generate an address signal.
Claim 5
Dependent Claim
25 words
The system of claim 1 wherein said second memory is responsive to address signals generated by said test pattern controller to produce subsequent instruction signals.
Claim 6
Independent Claim
98 words
A method of generating a sequence of test vectors, comprising the steps of: storing a set of test vectors; storing a list of variables to be inserted in said test vector; storing a set of test pattern instructions; generating a first address signal for accessing one of said test vectors in response to a stored test pattern instruction; generating a second address signal for accessing one of said variables; and selectively employing one of said first and second address signals to access one of said test vectors or said variables in response to a stored test pattern instruction.
Claim 7
Independent Claim
98 words
A method of generating a sequence of test vectors, comprising the steps of: storing a set of test vectors; storing a list of variables to be inserted in said test vector; storing a set of test pattern instructions; generating a first address signal for accessing one of said test vectors in response to a stored test pattern instruction; generating a second address signal for accessing one of said variables; and selectively employing one of said first and second address signals to access one of said test vectors or said variables in response to a stored test pattern instruction.
Claim 8
Dependent Claim
31 words
The method of claim 5 further including the steps of storing a set of synchronizing signals and accessing said synchronizing signals in response to predetermined ones of said first address signals.
Claim 9
Dependent Claim
23 words
The method of claim 5 further including the step of accessing a subsequent test pattern instruction in response to said first address signal.
Claim 10
Dependent Claim
20 words
The method of claim 5 wherein said second address signal is generated in response to an accessed test pattern instruction.
Claim 11
Independent Claim
142 words
A method of generating a pattern of test vectors, comprising the steps of: storing a main sequence of test vectors, a subroutine of test vectors, and a list of test vector variables in a first memory; storing test sequence instructions in a second memory; indexing a register to a location relating to the address of a predetermined one of said test vector variables; generating an address signal to access one of the test sequence instructions in the second memory; generating a vector address signal in response to the accessed test sequence instruction; reading a test vector from the first memory in response to the vector address signal; and reading a test vector from the first memory in response to the indexed location of the register when a variable vector is to inserted into the pattern of test vectors read from the memory.
Claim 12
Independent Claim
142 words
A method of generating a pattern of test vectors, comprising the steps of: storing a main sequence of test vectors, a subroutine of test vectors, and a list of test vector variables in a first memory; storing test sequence instructions in a second memory; indexing a register to a location relating to the address of a predetermined one of said test vector variables; generating an address signal to access one of the test sequence instructions in the second memory; generating a vector address signal in response to the accessed test sequence instruction; reading a test vector from the first memory in response to the vector address signal; and reading a test vector from the first memory in response to the indexed location of the register when a variable vector is to inserted into the pattern of test vectors read from the memory.
Claim 13
Dependent Claim
23 words
The method of claim 9 wherein the vector address signal is applied to the second memory as the test sequence instruction address signal.
Claim 14
Dependent Claim
24 words
The method of claim 9 wherein the index location of the register is determined by the test sequence instructions stored in the second memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-08 | 1988-07-09 | 1989-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-08 | 1992-07-09 | 1993-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-08 | 1996-07-09 | 1997-01-08 | $7700.00 | Window Closed / Lapsed |