US4357703A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test system for LSI circuits resident on LSI chips
Assignee: MARHOEFER LAURENCE J
•
Filing: 1980-10-09
•
Granted: 1982-11-02
•
Expires: 2000-10-09
Abstract
Abstract A test system performs dynamic testing of complex logic modules at full system clock rates and is resident on each LSI chip under test. The system logic is designed to be included on each LSI chip to reduce the time and computation required to detect and isolate faults in systems built from one or more chips. The on chip system includes switchable transmission gates to alter logic paths, a control shift register in the test function, an input shift register, an associated test generator and accumulator, an output shift register and an associated generator and accumulator. This logic provides test operands for the logic function under test and analyzes the resultant operands. Test operands are produced using a shift register connected to all inputs of the logic function under test. Checksum logic together with a shift register produce a running checksum of all output states of the module under test at the operative clock rate of the LSI.
Inventors
- 👤 Nicholas P. Van Brunt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:38
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
312 words
An LSI chip logic testing system adapted to be resident on an LSI chip comprising: an LSI chip having chip functional inputs and chip functional outputs, a main logic functional circuit on said chip, said circuit having main logic functional inputs and main logic functional outputs, first transmission gate means on said chip switchably connecting the chip functional inputs to the main logic functional inputs, second transmission gate means switchably connecting the main logic functional outputs to the chip functional outputs, input shift register means for serially receiving and sending test data and for parallel connection with the main logic functional inputs of said main logic functional circuit, first generator and accumulator means connected with said input shift register means, third transmission gate means switchably connected between said main logic functional inputs and said input shift register means, fourth transmission gate means switchably connected to the main logic functional outputs, output shift register means connected to said fourth transmission gate means for serially receiving and sending test data and for parallel connection with the main logic functional outputs of said main logic functional circuit through said fourth transmission gate means, second generator and accumulator means connected with said output shift register means, control shift register means having control paths to said first through fourth transmission gate means for controlling the switching operation thereof, said control shift register means being further connected to said input shift register, said output shift register and said first and second generators and accumulators, a test data input termination means on said chip for connection externally, said test data input termination means being connected to said control shift register means, a test control input means connected externally to said chip and connected to said control shift register means, and a test data output termination means connected externally to said chip and connected to said control shift register means.
Claim 2
Dependent Claim
312 words
An LSI chip logic testing system adapted to be resident on an LSI chip comprising: an LSI chip having chip functional inputs and chip functional outputs, a main logic functional circuit on said chip, said circuit having main logic functional inputs and main logic functional outputs, first transmission gate means on said chip switchably connecting the chip functional inputs to the main logic functional inputs, second transmission gate means switchably connecting the main logic functional outputs to the chip functional outputs, input shift register means for serially receiving and sending test data and for parallel connection with the main logic functional inputs of said main logic functional circuit, first generator and accumulator means connected with said input shift register means, third transmission gate means switchably connected between said main logic functional inputs and said input shift register means, fourth transmission gate means switchably connected to the main logic functional outputs, output shift register means connected to said fourth transmission gate means for serially receiving and sending test data and for parallel connection with the main logic functional outputs of said main logic functional circuit through said fourth transmission gate means, second generator and accumulator means connected with said output shift register means, control shift register means having control paths to said first through fourth transmission gate means for controlling the switching operation thereof, said control shift register means being further connected to said input shift register, said output shift register and said first and second generators and accumulators, a test data input termination means on said chip for connection externally, said test data input termination means being connected to said control shift register means, a test control input means connected externally to said chip and connected to said control shift register means, and a test data output termination means connected externally to said chip and connected to said control shift register means.
Claim 3
Dependent Claim
30 words
The system of claim 1 wherein the chip functions in normal fashion with said first and second transmission gate means closed and said third and fourth transmission gate means open.
Claim 4
Dependent Claim
43 words
The system of claim 1 wherein a test monitoring operation is performed with said first through fourth transmission gate means closed, the main logic functional circuit operating normally, and said input and output shift registers sampling input and output operands at selected times.
Claim 5
Dependent Claim
53 words
The system of claim 1 wherein a test function is performed with said first transmission gate means open and said second through fourth transmission gate means closed and wherein said third transmission gate means is connected in the input data path between said first transmission gate means and the main logic functional circuit.
References Cited (Backward Citations)
US3614608A
Cited
US3723868A
Cited
US3777129A
Cited
US3927371A
Cited
US4176258A
Cited
US4244048A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-01 | 1986-05-03 | 1986-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-01 | 1990-05-03 | 1990-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-01 | 1994-05-03 | 1994-11-02 | $7700.00 | Window Closed / Lapsed |