Random number statistical logic test system

Claim 1

A system for testing a complex functional logic circuit having a plurality of connecting terminals said system comprising: a reference logic circuit having functional properties identical to that of the logic circuit under test; means for generating a random test pattern including: a first shift register for generating a pseudo-random signal pattern, a second shift register for generating a gating pattern, and gating means for gating the pseudo-random signals to a plurality of correspOnding input terminals in both logic circuit under test and said reference logic; and a logic compare unit for receiving signals from the logic circuit under test and the reference logic circuit, and for providing an error output when any corresponding two of said signals differ.

Claim 2

A system for testing a complex functional logic circuit having a plurality of connecting terminals said system comprising: a reference logic circuit having functional properties identical to that of the logic circuit under test; means for generating a random test pattern including: a first shift register for generating a pseudo-random signal pattern, a second shift register for generating a gating pattern, and gating means for gating the pseudo-random signals to a plurality of correspOnding input terminals in both logic circuit under test and said reference logic; and a logic compare unit for receiving signals from the logic circuit under test and the reference logic circuit, and for providing an error output when any corresponding two of said signals differ.

Claim 6

A system for testing a complex functional logic circuit having a plurality of input and output terminals, said system comprising: a reference logic circuit having the same functional properties as the logic circuit under test; means for generating a random test pattern for application to each of the input terminals of the logic under test and the reference logic circuit; means for biasing the output terminals of the logic under test through an impedance to a desired termination level; analog means for converting the signals from the output terminals of the logic under test to two distinct digital signals; and comparing means for comparing the said two distinct digital signals with digital signals from corresponding output terminals of said reference logic circuit.

Claim 7

A system for testing a complex functional logic circuit having a plurality of input and output terminals, said system comprising: a reference logic circuit having the same functional properties as the logic circuit under test; means for generating a random test pattern for application to each of the input terminals of the logic under test and the reference logic circuit; means for biasing the output terminals of the logic under test through an impedance to a desired termination level; analog means for converting the signals from the output terminals of the logic under test to two distinct digital signals; and comparing means for comparing the said two distinct digital signals with digital signals from corresponding output terminals of said reference logic circuit.

Claim 8

A system for testing a complex functional logic circuit having a plurality of inputs and outputs, said system comprising: a reference logic circuit having functional properties comparable to those of the logic circuit under test; means for generating a random test pattern for application to selected ones of the inputs to the logic circuit under test and the reference logic circuit; means for biasing the outputs of the logic circuit under test through an impedance to a desired termination level; analog means for converting the signals from the outputs of the logic circuit under test to two distinct digital signals; and comparing means for comparing the two distinct digital signals with digital signals from corresponding outputs of said reference logic circuit.

Claim 9

A system for testing a complex functional logic circuit having a plurality of inputs and outputs, said system comprising: a reference logic circuit having functional properties comparable to those of the logic circuit under test; means for generating a random test pattern for application to selected ones of the inputs to the logic circuit under test and the reference logic circuit; means for biasing the outputs of the logic circuit under test through an impedance to a desired termination level; analog means for converting the signals from the outputs of the logic circuit under test to two distinct digital signals; and comparing means for comparing the two distinct digital signals with digital signals from corresponding outputs of said reference logic circuit.

Claim 11

The method of sequentially testing a plurality of identical logic circuits each having a plurality of access terminals, comprising the steps of: generating a random test pattern; applying said generated random test pattern to a first one of said plurality of identical logic circuits under test for a fixed interval of time; determining the analog levels of the output terminals of the logic circuit under test; converting the analog levels to digital levels; comparing the digital levels of the response from the logic under test to the response from corresponding terminals of a reference logic circuit; applying said generated random test pattern to additional ones of said plurality of identical logic circuits under test for additional fixed intervals of time; and repeating the foregoing steps of determining, converting, and comparing with respect to said additional ones of said plurality of identical logic circuits; whereby after a large number of plurality of identical logic circuits have been thus tested, a condition where all possible combinations of said random test pattern being applied to said plurality of identical logic circuits is approached.

Claim 12

The method of sequentially testing a plurality of identical logic circuits each having a plurality of access terminals, comprising the steps of: generating a random test pattern; applying said generated random test pattern to a first one of said plurality of identical logic circuits under test for a fixed interval of time; determining the analog levels of the output terminals of the logic circuit under test; converting the analog levels to digital levels; comparing the digital levels of the response from the logic under test to the response from corresponding terminals of a reference logic circuit; applying said generated random test pattern to additional ones of said plurality of identical logic circuits under test for additional fixed intervals of time; and repeating the foregoing steps of determining, converting, and comparing with respect to said additional ones of said plurality of identical logic circuits; whereby after a large number of plurality of identical logic circuits have been thus tested, a condition where all possible combinations of said random test pattern being applied to said plurality of identical logic circuits is approached.

Claim 13

The method of sequentially testing a plurality of identicaL logic circuits each having a plurality of access terminals, comprising the steps of: simulating a reference logic circuit having the same functional properties as each of the plurality of identical logic circuits under test; generating a random test pattern; applying said generated random test pattern to a first one of said plurality of identical logic circuits under test for a fixed interval of time; determining the analog levels of the output terminals of the logic circuit under test; converting the analog levels to digital levels; comparing the digital levels of the response from the logic under test to the response from corresponding terminals of said simulated reference logic circuit; applying said generated random test pattern to additional ones of said of identical logic circuits under test for additional fixed intervals of time; and repeating the foregoing steps of determining, converting, and comparing with respect to said additional ones of said plurality of identical logic circuits; whereby after a large number of said plurality of identical logic circuits have been thus tested, a condition where all possible combinations of said random test pattern being applied to said plurality of identical logic circuits is approached.

Claim 14

The method of sequentially testing a plurality of identicaL logic circuits each having a plurality of access terminals, comprising the steps of: simulating a reference logic circuit having the same functional properties as each of the plurality of identical logic circuits under test; generating a random test pattern; applying said generated random test pattern to a first one of said plurality of identical logic circuits under test for a fixed interval of time; determining the analog levels of the output terminals of the logic circuit under test; converting the analog levels to digital levels; comparing the digital levels of the response from the logic under test to the response from corresponding terminals of said simulated reference logic circuit; applying said generated random test pattern to additional ones of said of identical logic circuits under test for additional fixed intervals of time; and repeating the foregoing steps of determining, converting, and comparing with respect to said additional ones of said plurality of identical logic circuits; whereby after a large number of said plurality of identical logic circuits have been thus tested, a condition where all possible combinations of said random test pattern being applied to said plurality of identical logic circuits is approached.