Fault detection and localization in digital systems

Claim 2

A fault detection arragement for n circuit paths, each extending from a first point to a second point, comprising: means for applying a predetermined set of tests to said paths at said first point; a testing circuit having an input individual to each of said n circuit paths and one output; means for connecting each input of said testing circuit to its corresponding circuit path at said second point; means for storing an output pattern corresponding to a no circuit fault condition; and means for comparing the output pattern from said one output resulting from the application of said predetermined set of tests with said output pattern corresponding to a no circuit fault condition, a disagreement therebetween indicating a faulty circuit path.

Claim 3

The fault detection arrangement of claim 1 wherein each test of said set of tests includes n binary inputs, one for each of said n circuit paths, and the application of each of said tests to said circuit paths at said first point results in a single binary output from said testing circuit.

Claim 4

The fault detection arrangement of claim 2 wherein said binary inputs of each said test are simultaneously applied to their corresponding circuit paths at said first point.

Claim 5

A fault isolation arrangement for n circuit paths, each extending from a first point to a second point, comprising: means for applying a predetermined set of tests to said paths at said first point; a testing circuit having an input individual to each of said n circuit paths and one output; means for connecting each input of said testing circuit to its corresponding circuit path at said second point; means for storing output patterns corresponding to the no fault condition, and to possible fault conditions on each of said n paths and said one output; and means for comparing the output pattern from said one output resulting from the application of said predetermined set of tests to said paths at said first point with said output patterns corresponding to said no fault and possible fault conditions to ascertain the presence of a fault and to isolate any existing fault corresponding to said possible fault conditions.

Claim 6

A fault isolation arrangement for n circuit paths, each extending from a first point to a second point, comprising: means for applying a predetermined set of tests to said paths at said first point; a testing circuit having an input individual to each of said n circuit paths and one output; means for connecting each input of said testing circuit to its corresponding circuit path at said second point; means for storing output patterns corresponding to the no fault condition, and to possible fault conditions on each of said n paths and said one output; and means for comparing the output pattern from said one output resulting from the application of said predetermined set of tests to said paths at said first point with said output patterns corresponding to said no fault and possible fault conditions to ascertain the presence of a fault and to isolate any existing fault corresponding to said possible fault conditions.

Claim 7

The fault isolation arrangement of claim 4 wherein each test of said set of tests includes n binary inputs, one for each of said n circuit paths, and the application of each of said tests to said circuit paths at said first point results in a single binary output from said testing circuit.

Claim 8

The fault isolation arrangement of claim 5 wherein said n binary inputs of each said test are simultaneously applied to their corresponding circuit paths at said first point.

Claim 9

The fault isolation arrangement as claimed in claim 4 wherein the minimum number of tests P required to isolate a failure to any one of said n-inputs is expressed by the relationship: 2P 2 -1 < or = n < or = 2P 1 - 2.

Claim 10

In an integrated circuit assembly having a circuit chip including terminal pads, external terminals and bonding leads for connecting said external terminals to said terminal pads, a testing circuit for detecting electrical faults between predetermined ones of said external terminals and their corresponding terminal pads, said testing circuit having an input individual to each of said corresponding terminal pads and an output, and said testing circuit representing a function derived from a test procedure having a normal output vector including at least one logic one and one logic zero, and a set of input vectors, each of said input vectors having at least one logic one and one logic zero.

Claim 11

In an integrated circuit assembly having a circuit chip including terminal pads, external terminals and bonding leads for connecting said external terminals to said terminal pads, a testing circuit for detecting electrical faults between predetermined ones of said external terminals and their corresponding terminal pads, said testing circuit having an input individual to each of said corresponding terminal pads and an output, and said testing circuit representing a function derived from a test procedure having a normal output vector including at least one logic one and one logic zero, and a set of input vectors, each of said input vectors having at least one logic one and one logic zero.

Claim 12

In an integrated circuit assembly having a circuit chip including terminal pads, external terminals and bonding leads for connecting said external terminals to said terminal pads, a testing circuit for isolating electrical faults occurring between predetermined ones of said external terminals and their corresponding terminal pads, said testing circuit having an input individual to each of said corresponding terminal pads and an output, and said testing circuit representing a function derived from a test procedure having a normal output vector including at least one logic one and one logic zero, and a set of separable input vectors, each of said input vectors including at least one logic one and one logic zero, and each of said input vectors being separable from said normal output vector.

Claim 13

In an integrated circuit assembly having a circuit chip including terminal pads, external terminals and bonding leads for connecting said external terminals to said terminal pads, a testing circuit for isolating electrical faults occurring between predetermined ones of said external terminals and their corresponding terminal pads, said testing circuit having an input individual to each of said corresponding terminal pads and an output, and said testing circuit representing a function derived from a test procedure having a normal output vector including at least one logic one and one logic zero, and a set of separable input vectors, each of said input vectors including at least one logic one and one logic zero, and each of said input vectors being separable from said normal output vector.