US3723868A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for testing electronic apparatus
Assignee: General Dynamics Corp
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Filing: 1972-01-21
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Granted: 1973-03-27
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Expires: 1992-01-21
Abstract
Abstract A printed circuit card tester for dynamically testing digital logic circuits on a visual GO/NO-GO basis is described. A repetitive set of waveforms is supplied to the circuit under test as stimuli therefor. Digital logic circuitry performs analysis of an output from the circuit under test which involved the counting of predetermined numbers of clock pulses during preselected timing intervals to determine the precise time interval between distinct edges (transitions) of the output from the circuit under test and to provide GO/NO-GO indications while the circuit under test is being dynamically exercised.
Inventors
- 👤 B Foster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 09:49
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31935
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
135 words
A system for testing electrical apparatus which comprises a. means for generating repetitive test signal and applying said signal to said apparatus so that said apparatus operates in response to said signal to produce a first output, b. first counter and a second counter, c. means for advancing said first counter at a predetermined rate, d. means for advancing said second counter in response to said output, e. means for providing second and third outputs respectively from said first and second counters respectively when said first and second counters are advanced to first and second counts, and f. means responsive to said second and third outputs for enabling a ''''go'''' indication when said second and third outputs occur simultaneously and for enabling a ''''no-go'''' indication when said second and third outputs do not occur simultaneously.
Claim 2
Independent Claim
135 words
A system for testing electrical apparatus which comprises a. means for generating repetitive test signal and applying said signal to said apparatus so that said apparatus operates in response to said signal to produce a first output, b. first counter and a second counter, c. means for advancing said first counter at a predetermined rate, d. means for advancing said second counter in response to said output, e. means for providing second and third outputs respectively from said first and second counters respectively when said first and second counters are advanced to first and second counts, and f. means responsive to said second and third outputs for enabling a ''''go'''' indication when said second and third outputs occur simultaneously and for enabling a ''''no-go'''' indication when said second and third outputs do not occur simultaneously.
Claim 3
Dependent Claim
40 words
The invention as set forth in claim 1 wherein said apparatus is an electrical circuit having multiple inputs and wherein said generating means includes means for generating a plurality of said test signals and applying them to said circuit inputs.
Claim 4
Dependent Claim
47 words
The invention as set forth in claim 2 wherein said electrical apparatus is a digital circuit and said means included in said generating means provides a plurality of square waves having transitions from high to low level which have different time relationships with respect to each other.
Claim 5
Dependent Claim
19 words
The invention as set forth in claim 1 including means responsive to said output for resetting said first counter.
Claim 6
Dependent Claim
37 words
The invention as set forth in claim 1 wherein said advancing means includes means for detecting transitions in said first output and generating a pulse for advancing said second counter upon detection of Each of said transitions.
Claim 7
Dependent Claim
112 words
The invention as set forth in claim 5 wherein said transition detecting means includes first and second flip-flops adapted to be in set or reset states when clocked depending upon the level of signal applied thereto being high or low, and having outputs which are high or low level depending upon the set or reset condition thereof, said first output being applied to the input of said first flip-flop, and said first flip-flop output being connected to said second flip-flop input, means for clocking said flip-flops at a first rate, and means for providing said pulse during each clock interval when said first and second flip-flops are not in the same state.
Claim 8
Dependent Claim
61 words
The invention as set forth in claim 6 wherein said pulse providing means is an exclusive OR gate input connected to said first and second flip-flop outputs, and a gate having separate inputs for receiving input pulses at said clock pulse rate, pulses at a rate higher than said clock pulse rate, and for the output from said exclusive OR gate.
Claim 9
Dependent Claim
76 words
The invention as set forth in claim 1 wherein said means for providing said second and third outputs includes a first comparator and a second comparator, and first and second switching means for selectively inputting different digital numbers respectively into said first and second comparator corresponding to different counts whereby to enable said comparators to provide said second and third outputs when said first and second counters are advanced to store counts equal to said numbers.
Claim 10
Dependent Claim
57 words
The invention as set forth in claim 1 wherein said means for enabling said ''''go'''' and ''''no-go'''' indications comprise a first flip-flop and a second flip-flop, means for applying said second output to steer said flip-flops both to one state when strobed, and means for applying said third output to both said flip-flops to strobe said flip-flops.
Claim 11
Dependent Claim
77 words
The invention as set forth in claim 9 wherein said flips-flops each have complementary outputs, a ''''go'''' indicator, a ''''no-go'''' indicator, and means for coupling said ''''go'''' indicator and said ''''no-go'''' indicator respectively to one of the outputs of said first flip-flop and to one of the outputs of said second flip-flop, said one output of said first flip-flop being complementary to said one output of said second flip-flop when said flip-flops are in the same state.
Claim 12
Dependent Claim
95 words
The invention as set forth in claim 1 wherein said electrical apparatus is a digital circuit having a plurality of inputs and wherein said generating means includes means for generating a plurality of square wave test signals which have transitions in level between two levels which transitions in different ones of said test signals occur in certain time relationship, and said means for advancing said first counter includes means for applying clock pulses to said second counter having a period less than the shortest interval between the transitions of different ones of said test signals.
Claim 13
Dependent Claim
21 words
The invention as set forth in claim 11 including means for resetting said first counter when it reaches a predetermined count.
Claim 14
Dependent Claim
44 words
The invention as set forth in claim 11 including means for resetting said first and second counters after the end of the period between successive transitions of the one of test signals having the longest period between transitions of any of said test signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-26 | 1976-09-25 | 1977-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-26 | 1980-09-25 | 1981-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-26 | 1984-09-25 | 1985-03-27 | $7700.00 | Window Closed / Lapsed |