US4069510A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interrupt status register for interface adaptor chip
Assignee: Motorola Solutions Inc
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Filing: 1976-05-24
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Granted: 1978-01-17
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Expires: 1996-05-24
Abstract
Abstract A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, the data direction register and a data register. Data from the peripheral data bus the data direction register and the control register are transferred via the output bus to the data bus buffers. Control circuits include an interrupt/status logic circuit for transmitting control signals to and receiving interrupt signals from a peripheral unit coupled to the interface circuit.
Inventors
- 👤 Earl F. Carlow
- 👤 Michael F. Wiles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:22
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/38
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
261 words
In an interface adaptor for interfacing between a peripheral data bus coupled to a peripheral device and to a system data bus coupled to processor means for executing a plurality of instructions, interrupt circuitry comprising: an interrupt conductor for conducting an interrupt request signal from said peripheral device; interrupt circuit means coupled to said interrupt conductor means for receiving said interrupt request signal and generating an interrupt request output signal in response to said interrupt request signal; an interrupt output conductor coupled to said interrupt circuit means for conducting said interrupt request output signal; first storage circuit means responsive to said interrupt circuit means and coupled between said interrupt circuit means and said system data bus for receiving and storing interrupt request status information representative of whether or not any interrupt request signal has been received by said interrupt circuit means; a read conductor responsive to said processor means for conducting a read signal from said processor means to said interface adaptor; address conductors responsive to said processor means for cnducting address signals representative of the location of said first storage circuit means form said processor means to said interface adaptor means; address decoding means responsive to said address conductors for decoding said address signals to produce a selection signal; and means responsive to said selection signal and to said read signal and coupled to said first storage circuit means and to said system data bus for electrically coupling said first storage circuit means to said system data bus to effect reading said interrupt request status information by said processor means.
Claim 2
Dependent Claim
261 words
In an interface adaptor for interfacing between a peripheral data bus coupled to a peripheral device and to a system data bus coupled to processor means for executing a plurality of instructions, interrupt circuitry comprising: an interrupt conductor for conducting an interrupt request signal from said peripheral device; interrupt circuit means coupled to said interrupt conductor means for receiving said interrupt request signal and generating an interrupt request output signal in response to said interrupt request signal; an interrupt output conductor coupled to said interrupt circuit means for conducting said interrupt request output signal; first storage circuit means responsive to said interrupt circuit means and coupled between said interrupt circuit means and said system data bus for receiving and storing interrupt request status information representative of whether or not any interrupt request signal has been received by said interrupt circuit means; a read conductor responsive to said processor means for conducting a read signal from said processor means to said interface adaptor; address conductors responsive to said processor means for cnducting address signals representative of the location of said first storage circuit means form said processor means to said interface adaptor means; address decoding means responsive to said address conductors for decoding said address signals to produce a selection signal; and means responsive to said selection signal and to said read signal and coupled to said first storage circuit means and to said system data bus for electrically coupling said first storage circuit means to said system data bus to effect reading said interrupt request status information by said processor means.
Claim 3
Dependent Claim
61 words
Interrupt circuitry as recited in claim 1 further comprising second storage means coupled between said data bus means and said interrupt circuit means for receiving an interrupt enable bit from said system data bus and storing said interrupt enable bit and enabling said interrupt circuit means to generate said interrupt request output signal in response to said stored interrupt enable bit.
Claim 4
Dependent Claim
35 words
The interrupt circuitry as recited in claim 1 wherein said first storage circuit means includes a flip-flop coupled between said interrupt circuit means and said system data bus for storing said interrupt request status information.
Claim 5
Dependent Claim
33 words
The interrupt circuitry as recited in claim 2, wherein said second storage means includes a flip-flop coupled between said data bus means and said interrupt circuit means for storing said interrupt enable bit.
Claim 6
Dependent Claim
72 words
The interrupt circuitry as recited in claim 2 wherein said interrupt circuit means further includes gating circuit means having an output coupled to said interrupt output conductor means, and having an input coupled to an output of said second storage means and having another input coupled to said interrupt conductor means, for enabling said interrupt circuit means to generate said interrupt request output signal in response to said stored interrupt enable bit.
Claim 7
Independent Claim
196 words
A method of operating an interface adaptor system, said interface adaptor system including a first interface adaptor coupled to a system data bus and to a first peripheral data bus for electrically interfacing between said system data bus and said first peripheral data bus, said first interface adaptor also being connected to an interrupt request output conductor and to a first interrupt request input conductor for conducting an interrupt request signal to said first interface adaptor, said interface adaptor system further including a second interface adaptor coupled to said system data bus and to said interrupt request output conductor and to a second peripheral data bus for electrically interfacing between said system data bus and said second peripheral data bus, said second interface adaptor being also coupled to a second interrupt request input conductor, said method comprising the steps of: conducting an interrupt request signal on one of said first and second interrupt request input conductors to one of said first and second interface adaptors; storing interrupt request status information in one of said first and said second interface adaptors representative of said occurrence of said interrupt request signal in response to said interrupt request signal;
Claim 8
Independent Claim
196 words
A method of operating an interface adaptor system, said interface adaptor system including a first interface adaptor coupled to a system data bus and to a first peripheral data bus for electrically interfacing between said system data bus and said first peripheral data bus, said first interface adaptor also being connected to an interrupt request output conductor and to a first interrupt request input conductor for conducting an interrupt request signal to said first interface adaptor, said interface adaptor system further including a second interface adaptor coupled to said system data bus and to said interrupt request output conductor and to a second peripheral data bus for electrically interfacing between said system data bus and said second peripheral data bus, said second interface adaptor being also coupled to a second interrupt request input conductor, said method comprising the steps of: conducting an interrupt request signal on one of said first and second interrupt request input conductors to one of said first and second interface adaptors; storing interrupt request status information in one of said first and said second interface adaptors representative of said occurrence of said interrupt request signal in response to said interrupt request signal;
Claim 9
Dependent Claim
68 words
producing an interrupt request output signal on said interrupt request output conductor in response to said interrupt request signal; interrogating said first and second interface adaptors in a predetermined order to determine which of said first and second interface adaptors contains said stored information; and transmitting a signal representative of said stored information from said one of said first and second interface adaptors onto said system data bus.
Claim 10
Dependent Claim
68 words
producing an interrupt request output signal on said interrupt request output conductor in response to said interrupt request signal; interrogating said first and second interface adaptors in a predetermined order to determine which of said first and second interface adaptors contains said stored information; and transmitting a signal representative of said stored information from said one of said first and second interface adaptors onto said system data bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-16 | 1981-07-18 | 1982-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-16 | 1985-07-18 | 1986-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-16 | 1989-07-18 | 1990-01-17 | $7700.00 | Window Closed / Lapsed |