Interrupt sequencing control apparatus

Claim 2

Interrupt sequencing apparatus coupled in a system having a data processor connected to provide interrupt service in response to an interrupt signal from any one of a plurality of devices, said devices connected in an interrupt priority arrangement, said apparatus comprising: A. means, included in each of said devices, for generating said interrupt signal indicating that said respective device is ready to request interrupt service from said processor; B. interrupt priority means, coupled with each of said devices, for enabling the interrupt signal from the highest priority device; C. means, responsive to the enabled interrupt signal from the highest priority device of said devices, for receiving an indication of the commencement of interrupt service for the highest priority device generating said interrupt signal; D. means, included in each of said devices, for storing said interrupt signals generated either before or after said means for receiving provides the indication of the commencement of said interrupt service; and E. means, responsive to the completion of the interrupt service of said highest priority device generating said interrupt signal, for enabling the highest priority device which has stored an interrupt signal to request interrupt service from said processor.

Claim 3

Apparatus as in claim 1 further comprising: A. means for suspending the interrupt service with the one of said devices which is currently being serviced when said interrupt signal is generated by a device having a higher priority than said device currently being serviced by said processor; and B. means for automatically enabling the resumption of the interrupt service for said device whose interrupt service has been suspended upon the completion of the interrupt service by said processor for said device having said higher priority.

Claim 4

Apparatus as in claim 2 further comprising means for changing the state of said higher priority device to a state which indicates that said higher priority device is not ready for interrupt service by said processor, said means for changing responsive to the completion of interrupt service of said higher priority device and said means for changing not affecting the state of any other device.

Claim 5

Apparatus as in claim 3 wherein any one of said devices is capable of any one of four states including inactive, active, request and active states, said states indicated or generated in response to the following means, including: A. first means, including said means for changing, for placing any one of said devices in the inactive state when the device is not ready for interrupt service by saiD processor; B. second means, responsive to the readiness of the respective device for interrupt service by said processor, for placing said respective device in the wait state; C. third means, responsive to the readiness of the respective device for interrupt service and a signal indicating that said processor will service an interrupt request, for placing the respective device in the request state; and D. fourth means, responsive to the respective device in the request state and to a signal indicating that said respective device is the highest priority device, for placing said device in the active state thereby enabling interrupt service of said respective device by said processor.

Claim 6

Apparatus as in claim 4 wherein said interrupt priority means for each of said devices includes: A. means for receiving a priority indication signal from another device; B. means for inhibiting said device if said priority indication signal indicates that another device is the highest priority device which is ready for interrupt service; and C. means for enabling said device to be serviced if said priority indication signal indicates that there are no other higher priority devices which are ready to be serviced.

Claim 7

Apparatus as in claim 5: A. wherein said second means for placing includes a first bistable storage means having an output coupled for indicating that said respective device is in the wait state; B. wherein said third means for placing includes a second bistable storage means having an output coupled for indicating that said respective device is in the request state; and C. wherein said fourth means for placing includes a third bistable storage means having an output for indicating that said respective device is in the active state.

Claim 8

Apparatus in claim 6 wherein said means for generating said interrupt signal includes gate means enabled in respnse to the indication of said request state from the output of said second bistable storage means and to said signal indicating that said respective device is the highest priority device which is ready for service.

Claim 9

Interrupt sequencing apparatus coupled in a system having a data processor connected to provide interrupt service with any one of a plurality of devices, said devices connected in an interrupt priority arrangement, said apparatus included in each of said devices, said system comprising: A. bus means for coupling said devices in accordance with their respective interrupt priorities; said apparatus comprising B. means for receiving a device ready signal, said signal indicating that the respective device is ready to transfer data; C. first bistable means, responsive to said device ready signal, for generating a signal indicating that said respective device is in a wait state; D. second bistable means, responsive to the simultaneous presence of both said signal indicating that said respective device is in said wait state and a signal indicating that said processor will allow the interrupt servicing, for generating a signal indicating that said respective device is in a request state; E. first gate means, responsive to the simultaneous presence of both said signal indicating that said respective device is in said request state and to a signal indicating that said respective device is the highest priority device in the request state, said last mentioned signal coupled for receipt from said bus means, for providing an interrupt request signal to said processor; F. second gate means, responsive to the simultaneous presence of an acknowledgement signal from said processor in response to said interrupt request signal and to said signal indicating that said respective device is in the request state and to said signal indicating that said respective device is the highest priority device, for generating an enabling signal; and G. third bistable means, responsive to said enabling signal, for generating a signal indicatIng that said respective device is in the active state.

Claim 10

Interrupt sequencing apparatus coupled in a system having a data processor connected to provide interrupt service with any one of a plurality of devices, said devices connected in an interrupt priority arrangement, said apparatus included in each of said devices, said system comprising: A. bus means for coupling said devices in accordance with their respective interrupt priorities; said apparatus comprising B. means for receiving a device ready signal, said signal indicating that the respective device is ready to transfer data; C. first bistable means, responsive to said device ready signal, for generating a signal indicating that said respective device is in a wait state; D. second bistable means, responsive to the simultaneous presence of both said signal indicating that said respective device is in said wait state and a signal indicating that said processor will allow the interrupt servicing, for generating a signal indicating that said respective device is in a request state; E. first gate means, responsive to the simultaneous presence of both said signal indicating that said respective device is in said request state and to a signal indicating that said respective device is the highest priority device in the request state, said last mentioned signal coupled for receipt from said bus means, for providing an interrupt request signal to said processor; F. second gate means, responsive to the simultaneous presence of an acknowledgement signal from said processor in response to said interrupt request signal and to said signal indicating that said respective device is in the request state and to said signal indicating that said respective device is the highest priority device, for generating an enabling signal; and G. third bistable means, responsive to said enabling signal, for generating a signal indicatIng that said respective device is in the active state.

Claim 11

Apparatus as in claim 8 further comprising means, responsive to a clear signal indicating the completion of the interrupt servicing between said respective device and said processor, for changing the state indicated by said third bistable means so that an inactive state of said respective device is indicated.

Claim 12

Apparatus as in claim 9 further comprising: A. means for coupling the signal indicating that said respective device is in the active state to change the states indicated by said first and second bistable means so that said signal indicating said wait and request state are no longer generated; and B. means for coupling said clear signal to said third bistable means so that said signal indicating said active state is no longer generated.

Claim 13

Apparatus as in claim 8 further comprising: A. means for suspending the interrupt servicing with said respective device in the active state when said interrupt signal is generated by another device having a higher priority than said respective device; and B. means for automatically resuming the interrupt servicing with said respective device whose transfer has been suspended upon the completion of the interrupt servicing between said higher priority device and said processor.