US3911409A
Expired / Lapsed
US
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Data processing interface system
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1974-04-23
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Granted: 1975-10-07
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Expires: 1994-04-23
Abstract
Abstract A data processor is coupled with a plurality of peripheral devices via interface units or boxes, each coupled to one or more of such peripheral devices. The data processor and interface boxes are coupled in a full duplex path coupled in a daisy chained or serial manner so that the interface box furthest from the processor along the path has the lowest priority. Data is transferred in cycles with one output word and a priority word being transferred from the processor during each cycle, and with at least one input word capable of being transferred to the processor during each cycle. Apparatus is included to select the interface box with which data transfer is to be made during a cycle, in response to the priority word of the preceding cycle.
Inventors
- 👤 Krzysztof Kowal
- 👤 Jr Leon S Malone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:11
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
156 words
A data processing system comprising: A. a data processor; B. a plurality of peripheral interface boxes; C. full duplex coupling means serially coupled between said data processor and said plurality of boxes in order to provide for the transfer of data between said data processor and at least one of said boxes, said transfer of data repetitively occurring in cycles during each of which cycles an output word is capable of being transferred and a priority word is transferred from said processor and two input words are capable of being transferred to said processor; D. means, responsive to said priority word and included in each of said boxes, for determining the box which will be allowed to transfer data with said processor during the next one of said cycles; E. means, included in each of said boxes, for enabling said box so determined to transfer data with said processor during said next one of said cycles.
Claim 2
Dependent Claim
156 words
A data processing system comprising: A. a data processor; B. a plurality of peripheral interface boxes; C. full duplex coupling means serially coupled between said data processor and said plurality of boxes in order to provide for the transfer of data between said data processor and at least one of said boxes, said transfer of data repetitively occurring in cycles during each of which cycles an output word is capable of being transferred and a priority word is transferred from said processor and two input words are capable of being transferred to said processor; D. means, responsive to said priority word and included in each of said boxes, for determining the box which will be allowed to transfer data with said processor during the next one of said cycles; E. means, included in each of said boxes, for enabling said box so determined to transfer data with said processor during said next one of said cycles.
Claim 3
Dependent Claim
26 words
output logic for converting first and second logical state signals provided by said boxes to first and second polarity currents respectively for transfer over said busses.
Claim 4
Dependent Claim
26 words
output logic for converting first and second logical state signals provided by said boxes to first and second polarity currents respectively for transfer over said busses.
Claim 5
Dependent Claim
161 words
an output bus coupled to receive data from said processor for transfer to said boxes; F. means, included in each of said boxes, for receiving, during each of successive intervals of time, data from said output bus in the form of an output word and a priority word; G. first means, included in each of said boxes, for enabling the transfer, during each of said successive intervals of time, data to said input bus in the form of two input words; H. means, included in each of said boxes, for generating an interrupt request; I. means, included in each of said boxes, for detecting, during the time said priority word is being transferred, the highest priority interrupt requesting interface box; and J. second means, included in each of said boxes, for enabling said highest priority interrupt requesting box so determined, to transfer at least one input word to said processor during the next succeeding one of said successive intervals of time.
Claim 6
Dependent Claim
161 words
an output bus coupled to receive data from said processor for transfer to said boxes; F. means, included in each of said boxes, for receiving, during each of successive intervals of time, data from said output bus in the form of an output word and a priority word; G. first means, included in each of said boxes, for enabling the transfer, during each of said successive intervals of time, data to said input bus in the form of two input words; H. means, included in each of said boxes, for generating an interrupt request; I. means, included in each of said boxes, for detecting, during the time said priority word is being transferred, the highest priority interrupt requesting interface box; and J. second means, included in each of said boxes, for enabling said highest priority interrupt requesting box so determined, to transfer at least one input word to said processor during the next succeeding one of said successive intervals of time.
Claim 7
Dependent Claim
88 words
A system as in claim 1 wherein said means for enabling comprises means for transmitting at least one of said input words to said processor and wherein said system further comprises: A. means for receiving said output word in each of said boxes; B. means for determining the box for which said output word is intended; C. at least one peripheral unit coupled with each of said boxes; and D. means for transferring said output word from said box so determined to said at least one peripheral unit.
Claim 8
Dependent Claim
60 words
A system as in claim 2 wherein said box so determined is coupled to a plurality of peripheral units and further comprising: A. means for determining the one of said plurality of peripheral units for which said output word is intended; and B. means for transferring said output word from said box so determined to said peripheral unit so determined.
Claim 9
Dependent Claim
69 words
A system as in claim 2 further comprising: A. first interface means coupled between said processor and said coupling means for converting said words received from said processor from parallel by bit form to serial by bit form; and B. second interface means coupled between processor and said coupling means for converting said words received from said interface boxes from serial by bit form to parallel by bit form.
Claim 10
Dependent Claim
86 words
A data processing system comprising: A. a data processor; B. a plurality of peripheral units; C. a plurality of peripheral interface boxes; D. means for coupling each of said boxes for bidirectional transfer of data with one or more of said peripheral units; E. bus means for coupling said data processor in a serial, daisy chained manner with each of said boxes so that the box furthest away from said processor on said bus means has the lowest priority of said boxes, said bus means including
Claim 11
Dependent Claim
86 words
A data processing system comprising: A. a data processor; B. a plurality of peripheral units; C. a plurality of peripheral interface boxes; D. means for coupling each of said boxes for bidirectional transfer of data with one or more of said peripheral units; E. bus means for coupling said data processor in a serial, daisy chained manner with each of said boxes so that the box furthest away from said processor on said bus means has the lowest priority of said boxes, said bus means including
Claim 12
Dependent Claim
77 words
A system as in claim 5 further comprising means for providing each of said words on said busses in serial by bit form, a bit of a first logical state represented by a first polarity current, a bit of a second logical state represented by a second polarity current, and no current representing a gap, said gap occurring between each of said intervals of time and between the transfer of said output word and said priority word.
Claim 13
Dependent Claim
43 words
A system as in claim 6 wherein each of said interface boxes comprises: A. receive logic for receiving data from said processor; B. transmit logic for transmitting data to said processor; and wherein C. said receive logic and said transmit logic each include
Claim 14
Dependent Claim
68 words
A system as in claim 7 wherein said input logic comprises: A. impedance matching means coupled to receive the respective bus; B. first isolator means; and C. second isolator means, said first and second isolator means operative to generate the respective one of said logical state signals in response to the respective currents received from the respective one of said busses by means of said impedance matching means.
Claim 15
Dependent Claim
71 words
A system as in claim 7 wherein said receive logic comprises: A. means for detecting the transfer of an output word from said processor; and B. means, responsive to the detection of the transfer of said output word, for enabling the transfer of said output word from said input logic to said output logic and serially through the respective interface boxes so that each of said boxes receives said output word.
Claim 16
Dependent Claim
82 words
A system as in claim 9 wherein said receive logic further comprises: A. a shift register; B. means, responsive to the detection of the transfer of said output word, for shifting said output word into said shift register; C. means for indicating the one of said interface boxes for which said output word is intended; and D. means for transferring a portion of the contents of said output word from the intended one of said boxes to one of said peripheral units.
Claim 17
Dependent Claim
50 words
A system as in claim 10 wherein said receive logic further comprises: A. means for checking the parity of said output word received in said shift register; and B. means for disabling the transfer of said output word to said one of said peripheral units if said parity is incorrect.
Claim 18
Dependent Claim
47 words
A system as in claim 11 wherein said receive logic further comprises: A. means, responsive to the absence of either said first or second polarity current, for generating a gap signal; and B. means, responsive to said gap signal, for distinguishing between said successive intervals of time.
Claim 19
Dependent Claim
28 words
A system as in claim 12 wherein said receive logic further comprises means, responsive to said gap signal, for distinguishing between said output word and said priority word.
Claim 20
Dependent Claim
72 words
A system as in claim 7 wherein said transmit logic comprises: A. a shift register; B. means for loading data in bit parallel form from one of said peripheral units into said shift register; and C. means, responsive to the transfer of either an output word or a priority word for shifting said data from said register so as to provide said data as one of said input words to said processor.
Claim 21
Dependent Claim
45 words
A system as in claim 14 wherein said transmit logic further comprises: A. means for detecting a gap condition; and B. means, responsive to said gap condition, for enabling an error condition to be tRansferred to said processor from any one of said interface boxes.
Claim 22
Dependent Claim
82 words
A system as in claim 14 wherein said transmit logic further comprises means, included in said second means for enabling and responsive to said gap condition, for disabling or open circuiting said input bus between said highest priority interrupt requesting box and the other ones of said boxes further away on said input bus from said processor, so that said highest priority interrupt requesting box may transfer at least one input word to said processor during said next successive interval of time.
Claim 23
Dependent Claim
95 words
A system as in claim 5 wherein said priority word as received from said processor has a first signal state and further comprising means, included in each of said interface boxes, for changing said first signal state of said priority word to a second signal state, said changing of said first state to said second state occurring only in said highest priority interrupt requesting interface box, wherein said second signal state indicates to the ones of said boxes further away on said bus that another interface box has priority for data transfer with said processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-06 | 1979-04-07 | 1979-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-06 | 1983-04-07 | 1983-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-06 | 1987-04-07 | 1987-10-07 | $7700.00 | Window Closed / Lapsed |