Universal interface system using a controller to adapt to any connecting peripheral device

Claim 2

In a data processing system including a plurality of peripheral devices and a controller for providing a procedural adaptation stage for the peripheral devices and for receiving, processing and transmitting data signals to said peripheral devices, said controller comprising: an instruction decode unit for depending instruction signals upon activation and responsive thereto to issue a plurality of command signals; a port unit including a plurality of input/output ports and a port register, each port having a plurality of bidirectional leads, selective groups of leads from one or more ports interconnecting said port register to each peripheral device, each of said plurality of input/output ports selectively activated by a first of said plurality of command signals to store the data signals in said port register for the peripheral device; an interrupt address generator connected to said port Unit for generating an instruction signal representative of requests by the peripheral devices for access to the controller in response to a second of said plurality of command signals; a counter receiving a third of said plurality of command signals from said instruction decode unit to load said counter, said counter counting set time signal pulses and generating an interrupt signal upon reaching a selected count; said instruction decode unit responsive to the interrupt signal to decode the instruction signal from said interrupt address generator to issue the first command signal to transmit the data signals from said port register to the peripheral device and to store the third command signal in said counter; a memory store having addressable storage locations responsive to address signals for delivering data and instruction signals stored therein, said interrupt address generator generating said address signals for the retrieval of the data and instruction signals; a working register connected to store a portion of the instruction signal from said memory store; and means connected to receive data signals from said memory store and to receive the portion of the instruction signal from said working register and responsive thereto to perform logical functions therewith and obtain resultant signals therefrom upon activation by a fifth of said plurality of command signals; said resultant signals being directed to said port register to transmit said resultant signals from the input/output ports activated by said first command signal for transmission as data signals to the peripheral devices, said instruction decode unit generating said first and fifth command signals to activate or deactivate certain of said bidirectional leads of said input/output ports by the resultant signals.

Claim 3

A data processing system as defined in claim 1 wherein said instruction decode unit is responsive to the interrupt signal to decode unit is responsive to the interrupt signal to decode the instruction signal from said interrupt address generator to issue a fourth of said plurality of command signals to activate said port unit and selected input/output ports to accept data signals into said port unit from the peripheral device connected to the selected input/output ports for usage by the controller.

Claim 4

A data processing system as defined in claim 1 wherein said counter is a decrementing counter and the interrupt signal is generated when said counter reaches a count of zero.

Claim 5

A data processing system as defined in claim 1 wherein means is an said arithmetic and logical unit connected to receive data signals from the input/output ports activated by said first command signal, said arithmetic and logical unit in response to the fifth command signal performing logical functions on the data signals from said input/output port in combination with the instruction signals from said working register to obtain a second resultant signal therefrom, said instruction decode unit through the instruction signal and the arithmetic and logical unit effectively obtaining the second resultant signal wherein certain of the data signals are selectively activated or deactivated by said arithmetic and logical unit thereby activating or deactivating certain of the bidirectional leads in the activate input/output ports according to the insruction signal, said resultant signals being directed to a storage register for usage by the controller.

Claim 6

A data processing system as defined in claim 1 wherein said interrupt address generator of said controller further includes a means for selectively masking thereby disabling selected ones of said request signals to prevent the generation of an interrupt signal resulting from said masked request signals.

Claim 7

In a data processing system including a plurality of peripheral devices and a controller for providing a procedural adaptation stage for the peripheral devices and for receiving, processing and transmitting data signals to said perIpheral devices, said controller comprising: a memory store having addressable storage locations responsive to address signals for delivering data and instruction signals stored therein; an instruction decode unit for decoding instruction signals received from said memory store and responsive thereto to issue a plurality of command signals; a port unit including a plurality of input/output ports and a port register, each port having a plurality of bidirectional leads, selective groups of leads from one or more ports interconnecting said port register to each peripheral device, each of said plurality of input/output ports selectively activated by a first of said plurality of command signals to transfer data signals in said port register to the peripheral device; an interrupt address generator connected to said port unit to receive and detect request signals representative of request by the peripheral devices for access to the controller and responsive thereto to generate an interrupt signal for interrupting a process being performed by the controller and to generate an address signal to said memory store in accordance with a preset priority scheme for each peripheral device requiring service when the process has been interrupted; said instruction decode unit responsive to the interrupt signal to decode the instruction signal received from said memory store in response to the address signal and generating a second of said plurality of command signals to transfer data signals to said port register and generating the first command signal to selectively activate the input/output ports to transfer the data information from the port register to the peripheral device; a working register connected to store a portion of the instruction signal from said memory store; and means connected to receive data signals from said memory store and to receive the portion of the instruction signal from said working register, said means performing an AND logical function on the data and instruction signals in response to a fourth of said plurality of command signals to generate a resultant signal; said resultant signal being directed to said port register to transmit said resultant signal from the input/output ports activated by said first command signal for transmission as data signals to the peripheral device, and instruction decode unit generating said first and fifth command signals to activate or deactivate certain of said bidirectional leads of said input/output ports according to the resultant signal.

Claim 8

In a data processing system including a plurality of peripheral devices and a controller for providing a procedural adaptation stage for the peripheral devices and for receiving, processing and transmitting data signals to said perIpheral devices, said controller comprising: a memory store having addressable storage locations responsive to address signals for delivering data and instruction signals stored therein; an instruction decode unit for decoding instruction signals received from said memory store and responsive thereto to issue a plurality of command signals; a port unit including a plurality of input/output ports and a port register, each port having a plurality of bidirectional leads, selective groups of leads from one or more ports interconnecting said port register to each peripheral device, each of said plurality of input/output ports selectively activated by a first of said plurality of command signals to transfer data signals in said port register to the peripheral device; an interrupt address generator connected to said port unit to receive and detect request signals representative of request by the peripheral devices for access to the controller and responsive thereto to generate an interrupt signal for interrupting a process being performed by the controller and to generate an address signal to said memory store in accordance with a preset priority scheme for each peripheral device requiring service when the process has been interrupted; said instruction decode unit responsive to the interrupt signal to decode the instruction signal received from said memory store in response to the address signal and generating a second of said plurality of command signals to transfer data signals to said port register and generating the first command signal to selectively activate the input/output ports to transfer the data information from the port register to the peripheral device; a working register connected to store a portion of the instruction signal from said memory store; and means connected to receive data signals from said memory store and to receive the portion of the instruction signal from said working register, said means performing an AND logical function on the data and instruction signals in response to a fourth of said plurality of command signals to generate a resultant signal; said resultant signal being directed to said port register to transmit said resultant signal from the input/output ports activated by said first command signal for transmission as data signals to the peripheral device, and instruction decode unit generating said first and fifth command signals to activate or deactivate certain of said bidirectional leads of said input/output ports according to the resultant signal.

Claim 9

A data processing system as defined in claim 6 wherein said controller further includes a counter receiving a third of said plurality of command signals from said instruction decode unit in accordance with said address signal to load a count into said counter, said counter counting set time signal and generating a special interrupt signal to said interrupt address generator upon reaching a selected count, said interrupt address generator responsive to said special interrupt signal to generate an address signal.

Claim 10

A data processing system as defined in claim 7 wherein said counter is a decrementing counter and the special interrupt signal is generated when said counter reaches a count of zero.

Claim 11

A data processing system as defined in claim 6 wherein said means is an arithmetic and logic unit connected to receive data signals from the input/output ports activated by said first command signals, said arithmetic and logical unit in response to the fourth command signal performing the AND logical function on the data signals from said input/output ports in combination with the instruction signals from said working register to obtain a second resultant signal therefrom, wherein certain of the data signals are selectively activated or deactivated by said arithmetic and logical unit according to the instruction signal thereby effectively activating or deactivating certain of the bidirectional leads in the activated input/output ports, said second Resultant signal being directed to a storage register for usage by the controller.

Claim 12

A data processing system as defined in claim 6 wherein said interrupt address generator of said controller further includes a means for selectively masking thereby disabling selected ones of said request signals to prevent the generation of an interrupt signal resulting from said masked request signals.

Claim 13

In a data processing system including a plurality of peripheral devices and a controller for providing a procedural adaptation stage for the peripheral devices and for receiving, processing and transmitting data signals to said peripheral devices, and controller comprising: a memory store having addressable storage locations responsive to address signals for delivering data and instruction signals stored therein; an instruction decode unit for decoding instruction signals received from said memory store upon activation and responsive thereto to issue a plurality of command signals; a port unit including a plurality of input/output ports and a port register, each port having a plurality of bidirectional leads, selective groups of leads from one or more ports interconnecting said port register to each peripheral device, each of said plurality of input/output ports selectively activated by a first of said plurality of command signals to transfer data signals in said port register to the peripheral devices; an interrupt address generator connected to said port unit to receive and detect request signals representative of request by the peripheral devices for access to the controller and responsive thereto to generate an interrupt signal for interrupting a process being performed by the controller and to generate an address signal to said memory store in accordance with a preset priority scheme for each peripheral device requiring service when the process has been interrupted; a working register connected to store a portion of the instruction signal from said memory store; and an arithmetic and logical unit connected to receive data signals and to receive the portion of the instruction signal from said working register; said instruction decode unit responsive to the interrupt signal to decode the instruction signal received from said memory store in response to the address signal and generating a second of said plurality of command signals to transfer data signals from said memory store and the instruction signals from said working register to said arithmetic and logical unit and to activate said arithmetic and logic unit to perform a logical function and thereby generate a resultant signal; said resultant signal being directed to said port register to transmit said resultant signal from the input/output ports when activated by said first command signal for transmission as data signals to the peripheral devices, said instruction decode unit generating said first and second command signals to activate or deactivate certain of said bidirectional leads of said input/output ports according to the resultant signal; said arithmetic and logical unit being connected to receive data signals from the input/output ports activated by said first command signals, said arithmetic and logical unit in response to the second command signal performing the logical function on the data signals from said input/output ports in combination with the instruction signals from said working register to obtain a second resultant signal therefrom, wherein certain of the data signals are selectively activated or deactivated by said arithmetic and logical unit according to the instruction signal thereby activating or deactivating certain of the bidirectional leads in the activated input/output ports, said second resultant signal being directed to a storage register for usage by the controller.

Claim 14

In a data processing system including a plurality of peripheral devices and a controller for providing a procedural adaptation stage for the peripheral devices and for receiving, processing and transmitting data signals to said peripheral devices, and controller comprising: a memory store having addressable storage locations responsive to address signals for delivering data and instruction signals stored therein; an instruction decode unit for decoding instruction signals received from said memory store upon activation and responsive thereto to issue a plurality of command signals; a port unit including a plurality of input/output ports and a port register, each port having a plurality of bidirectional leads, selective groups of leads from one or more ports interconnecting said port register to each peripheral device, each of said plurality of input/output ports selectively activated by a first of said plurality of command signals to transfer data signals in said port register to the peripheral devices; an interrupt address generator connected to said port unit to receive and detect request signals representative of request by the peripheral devices for access to the controller and responsive thereto to generate an interrupt signal for interrupting a process being performed by the controller and to generate an address signal to said memory store in accordance with a preset priority scheme for each peripheral device requiring service when the process has been interrupted; a working register connected to store a portion of the instruction signal from said memory store; and an arithmetic and logical unit connected to receive data signals and to receive the portion of the instruction signal from said working register; said instruction decode unit responsive to the interrupt signal to decode the instruction signal received from said memory store in response to the address signal and generating a second of said plurality of command signals to transfer data signals from said memory store and the instruction signals from said working register to said arithmetic and logical unit and to activate said arithmetic and logic unit to perform a logical function and thereby generate a resultant signal; said resultant signal being directed to said port register to transmit said resultant signal from the input/output ports when activated by said first command signal for transmission as data signals to the peripheral devices, said instruction decode unit generating said first and second command signals to activate or deactivate certain of said bidirectional leads of said input/output ports according to the resultant signal; said arithmetic and logical unit being connected to receive data signals from the input/output ports activated by said first command signals, said arithmetic and logical unit in response to the second command signal performing the logical function on the data signals from said input/output ports in combination with the instruction signals from said working register to obtain a second resultant signal therefrom, wherein certain of the data signals are selectively activated or deactivated by said arithmetic and logical unit according to the instruction signal thereby activating or deactivating certain of the bidirectional leads in the activated input/output ports, said second resultant signal being directed to a storage register for usage by the controller.

Claim 15

A data processing system as defined in claim 11 wherein said controller further includes a counter receiving a third of said plurality of command signals from said instruction dEcode unit in accordance with said address signal to load a count into said counter, said counter counting set time signal pulses and generating a special interrupt signal to said interrupt address generator upon reaching a selected count, said interrupt address generator responsive to said special interrupt signal to generate an address signal.

Claim 16

A data processing system as defined in claim 11 wherein said interrupt address generator of said controller further includes a means for selectively masking thereby disabling selected ones of said request signals to prevent the generation of an interrupt signal resulting from said masked request signals.

Claim 17

In a data processing system including a plurality of peripheral devices and a controller for providing a procedural adaptation stage for the peripheral devices and for receiving, processing and transmtting data signals to said peripheral devices, said controller comprising: a memory store having addressable storage locations responsive to address signals for delivering data and instruction signals stored therein; an instruction decode unit for decoding instruction signals from said memory store and responsive thereto to issue a plurality of command signals; a port unit including a plurality of input/output ports, each port having a plurality of bidirectional leads, selective groups of leads from one or more ports interconnecting said port unit to each peripheral device, each of said plurality of input/output ports selectively activated by a first of said plurality of command signals to transmit data signals to the peripheral device and by a second of said plurality of command signals to accept data signals from the peripheral device; an interrupt address generator connected to said port unit to receive and detect request signals representative of request by the peripheral devices for access to the controller and responsive thereto to generate an interrupt signal for interrupting a process being performed by the controller and to generate an address signal to said memory store in accordance with a preset priority scheme for each peripheral device requiring service when the process has been interrupted; said instruction decode unit responsive to the interrupt signal to decode the instruction signal from said memory store and generating the first or the second command signal according to the instruction to activate the number and specific input/output ports and whether to accept or transmit data signals; a working register connected to store a portion of the instruction signal from said memory store; and means connected to receive the portion of the instruction signal from said working register and to receive data signals from said memory store or said port unit for performing a logic AND function on the data and instruction signals in response to a fourth of said plurality of command signals to generate a resultant signal; said resultant signal being directed to said port unit to transmit said resultant signal from the input/output ports activated for transmission as data signals if the first command signal is enabled, said resultant signal being directed to a storage register if the second command signal is enabled, said instruction decode unit generating said first or second and said fourth command signals to activate or deactivate the data signal on certain of said bidirectional leads of said input/output ports to obtain the resultant signal.

Claim 18

In a data processing system including a plurality of peripheral devices and a controller for providing a procedural adaptation stage for the peripheral devices and for receiving, processing and transmtting data signals to said peripheral devices, said controller comprising: a memory store having addressable storage locations responsive to address signals for delivering data and instruction signals stored therein; an instruction decode unit for decoding instruction signals from said memory store and responsive thereto to issue a plurality of command signals; a port unit including a plurality of input/output ports, each port having a plurality of bidirectional leads, selective groups of leads from one or more ports interconnecting said port unit to each peripheral device, each of said plurality of input/output ports selectively activated by a first of said plurality of command signals to transmit data signals to the peripheral device and by a second of said plurality of command signals to accept data signals from the peripheral device; an interrupt address generator connected to said port unit to receive and detect request signals representative of request by the peripheral devices for access to the controller and responsive thereto to generate an interrupt signal for interrupting a process being performed by the controller and to generate an address signal to said memory store in accordance with a preset priority scheme for each peripheral device requiring service when the process has been interrupted; said instruction decode unit responsive to the interrupt signal to decode the instruction signal from said memory store and generating the first or the second command signal according to the instruction to activate the number and specific input/output ports and whether to accept or transmit data signals; a working register connected to store a portion of the instruction signal from said memory store; and means connected to receive the portion of the instruction signal from said working register and to receive data signals from said memory store or said port unit for performing a logic AND function on the data and instruction signals in response to a fourth of said plurality of command signals to generate a resultant signal; said resultant signal being directed to said port unit to transmit said resultant signal from the input/output ports activated for transmission as data signals if the first command signal is enabled, said resultant signal being directed to a storage register if the second command signal is enabled, said instruction decode unit generating said first or second and said fourth command signals to activate or deactivate the data signal on certain of said bidirectional leads of said input/output ports to obtain the resultant signal.

Claim 19

A data processing system as defined in claim 14 wherein said controller further includes a counter receiving a third of said plurality of command signals from said instruction decode unit in accordance with said address signal to load a count into said counter, said counter counting set time signal pulses and generating a special interrupt signal to said interrupt address generator upon reaching a selected count, said interrupt address generator responsive to said special interrupt signal to generate an address signal.

Claim 20

A data processing system as defined in claim 14 wherein said interrupt address generator of said controller further includes a means for selectively masking thereby disabling selected ones of said request signals to prevent the generation of an interrupt signal resulting from said masked request signals.